Chinese semiconductor thread II

tokenanalyst

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Shanghai Hejingli Joint Venture specializes in SOI silicon wafers​


Shanghai Hejing disclosed a major industrial layout at an institutional performance exchange meeting. The company will establish a joint venture to focus on the SOI silicon wafer track and plans to build a 12-inch SOI wafer production line in three phases, with a long-term annual capacity of 216,000 wafers. This will allow the company to enter the blue ocean market of high-end semiconductor silicon wafers and accelerate the domestic substitution of core silicon-based materials.

This SOI project will create industrial synergy with the Zhengzhou 12-inch epitaxial wafer production line. The second phase of the Zhengzhou 12-inch epitaxial production line will be put into operation in June, adding an annual capacity of 720,000 wafers. After reaching full capacity, the company's total 12-inch integrated epitaxial capacity will reach 1.2 million wafers. The mature large-size production line can provide mature process support for SOI R&D and mass production, effectively sharing equipment, R&D and operating costs, and significantly reducing the threshold for the mass production of high-end silicon wafers.

The continued expansion of AI computing power, new energy vehicles, and the communications radio frequency industry is driving a sustained increase in demand for SOI silicon wafers. Previously, domestic companies lacked stable local supply channels, posing a risk to the security of the supply chain. Shanghai Hejing has implemented a phased rollout of 216,000 SOI wafers, which will provide domestic downstream chip design and wafer manufacturing companies with a self-sufficient and controllable supply of high-end silicon wafers, alleviating overseas supply constraints.

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tokenanalyst

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Huada Jiutian Advanced Packaging EDA Platform Achieves Major Breakthrough​

On June 9, Huada Jiutian announced a major technological breakthrough on its investor interaction platform, stating that its advanced packaging EDA platform is now fully capable of supporting the design of high-end AI chips, GPUs, high-performance processors, and other chiplets.

In the key technology field of 3DIC (3D integrated circuits) in the post-Moore era, Huada Jiutian has proactively built a full-process solution covering the collaborative design and verification of heterogeneous integrated 3D chips, and is currently the only EDA provider in China with this full-process capability.

It is reported that Huada Jiutian's first Argus 3DIC physical verification platform fully supports 2.5D/3D heterogeneous integrated packaging design and can realize full-link physical verification from collaborative design to packaging.

The platform's unique 3D data weaving technology can complete full 3D data verification in one go, significantly shortening the end-to-end verification cycle of high-end 3D stacked chips.

In the advanced packaging design phase, Huada Jiutian's automatic routing tool Storm has been fully upgraded to an advanced packaging design platform.

The platform supports silicon-based and organic RDL processes, and also supports new processes such as silicon bridge + RDL heterogeneous integration, enabling large-scale interconnect wiring between multiple chips.

Financial reports show that Huada Jiutian achieved revenue of 1.325 billion yuan in 2025, of which EDA software sales accounted for 81.1% and R&D investment accounted for as high as 64.84% of revenue. Its products have served more than 700 well-known customers in China.​

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Design Technology Co-Optimization of a Hybrid Dual-κ Spacer Strategy for Sub-3-nm Nanosheet Gaafets and Circuits Performance Enhancement.​


State Key Laboratory of Fabrication Technologies for Integrated Circuits
Institute of Microelectronics of the Chinese Academy of Sciences

Abstract:​

Spacer engineering is crucial for advanced GAA devices. To overcome the limitations of conventional single-κ spacers, a hybrid dual-κ spacer strategy in nanosheet (NS) GAAFETs at 3 nm node is proposed. It employs higher-κ inner spacers for better drive current and low-κ outer spacers to reduce parasitic capacitance. This practical design is validated through device simulation and circuit-level analysis. The results demonstrate the best design with over 25% decrease in capacitance than single SiN spacer, 17.01% (PMOS)/10.00% (NMOS) increase in on-state current and 108% frequency improvement in ROs over mainstream approaches, providing a valuable guide for the industrial fabrication of GAA transistors at advanced nodes.​

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tokenanalyst

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Investigation of Channel Stress in Monolithic CFET with Different SiGe Sacrificial Layers for A7 Technology Node.​

State Key Laboratory of Fabrication Technologies for Integrated Circuits
Institute of Microelectronics of the Chinese Academy of Sciences

Abstract:​

In this paper, to investigate the channel stress of the top NFET and bottom PFET in monolithic complementary field-effect transistor (mCFET), the integrated process and the stress engineering are simulated by TCAD method. The results show that the Ge concentration in the SiGe sacrificial layer (SL) increases from 10% to 40%, and the channel tensile stress of the top NFET can increase by 3.49X. However, the bottom PFET requires SiGe SL with lower Ge concentration to promote the formation of channel compressive stress. Meanwhile, by increasing the thickness of SiGe SL on the top NFET, the channel tensile stress is further optimized, which also provides a key path for continuously improving the performance of mCFET.​

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tokenanalyst

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Hybrid 2T0C Cell with Oxide-Semiconductor/Silicon Transistors for Capacitor-Free DRAM​

School of Integrated Circuits
Beijing Advanced Innovation Center for Integrated Circuits

Abstract:​

Capacitor-free 2T0C memory, pivotal for surpassing conventional dynamic random-access memory (DRAM) scaling limits, is critical for embedded systems demanding high density and low power. This work directly addresses the critical challenges of all-silicon 2T0C DRAM cells — excessive area overhead and insufficient data retention. A novel hybrid 2T0C architecture is proposed, exploiting back-end-of-line (BEOL) compatible oxide semiconductors (OS) for 3-D integration: low-leakage OS-based write transistors are vertically stacked in the BEOL layers atop silicon read transistors. Simulations and layout analysis confirm ~50% cell area reduction versus planar OS-based 2T0C counterparts, while Si transistor with high on-state current increases the memory window by 46 times. This approach delivers actionable design guidelines and theoretical underpinnings for next-gen embedded DRAM, enabling breakthroughs in performance and energy efficiency.​

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Heated Ion Implantation Technology for FinFET Source Drain Extension Formation​


Shanghai Kingstone Semiconductor Joint Stock Co., Ltd.

Abstract:​

Room-temperature ion implantation for FinFET doping inevitably introduces severe lattice damage in the fin body, which degrades the electrical performance and structural reliability of FinFET devices. Thus, mitigating implantation-induced damage is critical for advancing FinFET technology. In this work, heated ion implantation is proposed and systematically investigated for the fabrication of lightly doped drain (LDD) regions in FinFETs. Phosphorus ion (P+) implantations were performed on bare silicon wafers at different temperatures, and the process efficacy was comprehensively evaluated via Thermal Wave (TW) analysis for lattice disorder characterization, sheet resistance (Rs) measurements for dopant activation assessment, secondary-ion mass spectrometry (SIMS) for dopant depth profile analysis, and transmission electron microscopy (TEM) for microstructural observation. The optimized heated implantation process was subsequently applied to FinFET device fabrication for LDD formation. Experimental results show that increasing the implantation temperature effectively eliminates lattice damage in the fin structure. In comparison with conventional room-temperature implantation, the proposed heated implantation achieves damage-free fin structures while maintaining satisfactory dopant activation efficiency and precise dopant profile control. This study verifies that heated ion implantation is a feasible and high-efficiency solution to alleviate implantation-induced damage and boost the performance of advanced FinFET devices.​

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tokenanalyst

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Tau law applied at transistor level?

Increasing NSFET Design Flexibility with SheetOpt™​

Huawei Technologies R&D

Abstract:​

SheetOpt™ is a new way to modulate device current by adjusting the number of active stacked sheets within a given fin height. It allows us to achieve speed comparable to high-performance designs using high-density libraries saving up to 13% of chip area and simplifying chip design. In addition, SRAM bit-cells may be optimized without incurred area penalty during transistors sizing: we demonstrate improvements in write trip point without read static noise margin degradation.​

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tokenanalyst

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AMEC developing real time etching metrology

Real-Time Virtual Metrology Modeling for Etch Rate Prediction​


Abstract:​

This paper addresses the problem of difficult real-time and non-destructive measurement of etching rate in semiconductor etching processes, and proposes a real-time virtual measurement (VM) model based on optical emission spectroscopy (OES) data. By capturing the nonlinear mapping relationship between plasma emission spectrum characteristics and etching rate, a soft measurement model is constructed with multivariate time-series OES data as input and etching rate as output. The core lies in obtaining the influence of key wavelength signals through feature selection algorithms, and ultimately predicting the accuracy and robustness through machine learning models. Experiments show that this model can effectively achieve online high-precision prediction of etching rate, providing support for process monitoring and closed-loop control.​

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tokenanalyst

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Despite being blacklisted Jinhua still advancing.

TriFocusNet: A Triple-Branch Focus-Attention Network for Hotspot Detection in LELE Double Patterning Process​


Fujian Jinhua Integrated Circuit Co., Ltd.,

Abstract:​

Hotspot detection is a critical challenge in modern semiconductor manufacturing due to increasingly complex fabrication processes. The LELE (Litho‑Etch‑Litho‑Etch) double patterning process introduces substantial difficulties as interactions between multiple exposures are non-trivial to model. Traditional CNN architectures struggle to capture these multi‑phase effects. In this paper, we propose TriFocusNet, a novel three‑branch deep learning framework that separately processes first litho mask (L1), second litho mask (L2), and final combined (L1+L2) layout. To enhance prediction accuracy, a pattern density map is introduced as auxiliary input, guiding the model to focus on densely patterned regions, and an attention mechanism specifically highlights the central area of interest. The three branches are adaptively fused to produce the final classification. Experiments demonstrate that TriFocusNet surpasses existing methods on public benchmark datasets, and achieves over 85% accuracy on in‑house industrial data. The results validate the efficacy of multi‑branch modeling and density‑aware attention for hotspot prediction in LELE double patterning processes.​

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tokenanalyst

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DSA for EUV free metal layers patterns.

Directed Self-Assembly for Fabricating Rectangular Nanostructures with Tunable Aspect Ratios for Sub-7 nm BEOL Metal Cut.​

Zhangjiang Laboratory, Extreme Technology Institute

Abstract:​

This work presents an elliptical guiding template-regulated block copolymer (BCP) directed self-assembly (DSA) strategy, to address the critical bottleneck of sharply narrowed lithography process window for sub-20 nm tip-to-tip (T2T) gaps in sub-7 nm node back-end-of-line (BEOL) metal cut. Using this scheme, we successfully fabricated rectangular holes with a short axis down to sub-20 nm, tunable aspect ratios from 1 to 5, and an optimal pattern rectangularity below 4 nm. Combined with the pattern inversion process, this approach is expected to provide a low-cost, EUV-free viable pathway for advanced node BEOL patterning, and to extend the capability of conventional 193 nm immersion (193i) lithography.​

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