Breakthrough in AI Computing: Xi'an Institute Achieves Key Silicon Photonic Milestones
The National Key Laboratory of Ultrafast Optical Science and Technology at the Xi'an Institute of Optics and Precision Mechanics (XIOPM), Chinese Academy of Sciences, has announced a series of groundbreaking achievements in silicon photonic interconnect chips. These innovations are designed to overcome the critical "power consumption wall" and "communication wall" currently hindering the scalability of AI large models and intelligent computing centers.
The research team has developed a complete silicon photonics technology system from core devices to system integration—that directly supports Co-Packaged Optics (CPO) architecture, positioning China as a key player in post-Moore's Law computing infrastructure.
1. High-Speed Optical Receivers
Device: Silicon-Germanium Avalanche Photodetector (Si-Ge APD).
Performance: Achieved an international-leading gain-bandwidth product of 7,564 GHz.
Capability: Successfully tested for high-speed signal reception ranging from 64 Gbps to 200 Gbps, significantly boosting receiving sensitivity in optical communication systems.
2. Advanced Optical Modulators
Microring Modulator: Delivered a single-channel transmission rate exceeding 400 Gbps.
Mach-Zehnder Modulators (MZMs): Developed several high-bandwidth variants, including a novel serpentine structure MZM that achieves efficient electro-optical conversion within a compact area of approximately 1 mm², ideal for high-density integration.
3. System-Level Integration & Massive Throughput
4. CMOS Electrical Support Chips
Technology Node: Developed at the 28nm CMOS process level, specifically designed for 3D integration with silicon photonics.
Bandwidth: Transmit and receive bandwidths both exceed 60 GHz.
Efficiency: Supports 200 Gbps PAM4 transmission and 280 Gbps reception, achieving an excellent energy efficiency of 0.67 pJ/bit and a density of 4.9 Tbps/mm².
These advancements mark a pivotal shift in semiconductor development trends, aligning with concepts like Huawei's "Tao (τ) Law," which emphasizes moving away from geometric miniaturization toward
latency compression. The developed components are directly adaptable to CPO architecture, allowing for compact packaging and low latency. As a single-engine solution exceeds 2 Tbps throughput with low power consumption, these chips address the bottleneck of traditional electrical interconnects in next-generation AI clusters. This release underscores China's continued breakthrough capabilities in high-end silicon photonic technologies, securing its position in the foundational layer of future supercomputing and AI infrastructure.
