I think when it says ideal performance, that would indicate they think it can do HVM at 28nm.
Chinese semiconductor thread II
- Thread starter vincent
- Start date
Liande Equipment: Sales orders for laminating process equipment for the tri-fold screen supply chain have been formed and shipped
Recently, Liande Equipment stated in an institutional survey that the company has provided an overall solution for bonding process equipment in the tri-fold screen supply chain, and has formed sales orders and shipped the products.
In the field of Mini/Micro LED, Liande Equipment has currently launched chip sorting equipment, chip expansion equipment, testing equipment, vacuum lamination equipment, chip mass transfer equipment, high-precision splicing equipment, etc.
In the semiconductor field, Liande Equipment mainly produces packaging and testing equipment for the semiconductor back-end process. The main products are COF flip-chip machines, semiconductor flip-chip machines, soft solder die bonders, eutectic die bonders, AOI inspection machines, lead frame laminating machines and other high-speed and high-precision semiconductor equipment. In the field of advanced packaging, the company has display driver chip bonding equipment and COF flip-chip equipment. This flip-chip equipment is a high-precision and high-speed advanced packaging equipment that uses eutectic + flip chip bonding process.
Zuolan Microelectronics' high-performance 5G RF filter project launched
On September 20, the launch ceremony of Zuolan Microelectronics' 5G RF filter component project was held at the Cloud Manufacturing Pilot Center. District Party Secretary Xu Xiaobo, District Party Committee Member and Development Zone (Qinglong Sub-district) Party Working Committee Secretary Zhou Haipeng, and District People's Congress Standing Committee Deputy Director Jin Mingjie attended the event.
The project will increase R&D investment, break through technical bottlenecks, launch more high-performance RF filter products with independent intellectual property rights, and create a comprehensive operation base integrating R&D, testing, and sales to meet the growing market demand.
Single-Component High-Resolution Dual-Tone EUV Photoresists Based on Precision Self-Immolative Polymers.
University of Science and Technology of China, Department of Polymer Science and Engineering, CHINA
Abstract
Electron beam (EB) and extreme ultraviolet (EUV) lithography are advanced techniques capable of achieving sub-10 nm resolutions, critical for fabricating next-generation nanostructures and semiconductor devices. However, developing EUV photoresists that meet all demands for resolution, line edge roughness (LER), and sensitivity (RLS) remains a significant challenge. Herein, we introduce high-performance photoresists based on single-component self-immolative polymers (SIPs) with inherent signal amplification via cascade degradation. These SIPs function as dual-tone photoresists under both EB and EUV lithography, with performance primarily determined by the exposure dose. Lithographic evaluations show that discrete SIPs provide significant improvements over disperse counterparts, achieving higher resolution and reduced LER. Specifically, a discrete SIP with a DP of 12 produces a line-space pattern with a resolution of approximately 18 nm and an LER of 1.8 nm, compared to 21 nm resolution and 2.5 nm LER for disperse SIPs. Additionally, these SIP-based photoresists, enriched with aromatic structures, exhibit excellent etch resistance. The single-component nature and potential to address the RLS trade-off underscore the promise of discrete SIPs for EUV lithography.
Oriental Crystal Source PanGen DMC completes verification based on rapid process feedback to detect potential bad spots in the layout in advance
With the evolution of technology nodes, the integrated circuit manufacturing process itself has become more and more complex, and it has become increasingly difficult for designers to have a comprehensive and systematic understanding of the process, resulting in the need for repeated iterations of new products during the process end tape-out, which has led to a long period of yield ramping, increasing the cost of production and extending the time it takes for products to be put on the market. According to McKinsey statistics, it currently takes about 12 to 18 months of repeated iterations in the semiconductor industry from tape-out to mass production to improve the yield of new products.
Based on the solid computational lithography platform PanGen® and rich industry practice experience, Oriental Crystal Source has innovatively developed the PanGen DMC® (Design Manufacturability Check) product. Its embedded D2C (Design To Contour) fast lithography feedback engine can package the full set of FAB OPC Recipe solutions in the form of an AI model, allowing users to quickly and accurately estimate the final morphology (Contour) of the Design on the silicon wafer based on the original Design, and thus predict potential risks in the design layout in advance.
Through verification, the prediction error is less than 1nm
The actual test results in a domestic advanced node FAB show that the difference between the predicted results and the actual results of Oriental Crystal Source PanGen DMC® on the full chip scale is less than 1nm in more than 99% of the layout positions, proving that its D2C fast lithography feedback engine can accurately capture the behavior of the entire OPC recipe and provide Contour results that are very close to the complete OPC recipe.
Defect capture rate exceeds 90%
In addition, as process technology becomes increasingly complex, it is difficult to include all aspects of the entire process with abstract rules alone. Therefore, a design layout that passes the rule-based DRC (Design Rule Check) check on the design side does not mean that it can perform well on the process side. PanGen DMC® can estimate the final lithography morphology of the design layout and provide direct feedback to the process side by using FAB lithography sign-off in advance. The actual measurement results in a domestic advanced node FAB show that DMC can predict serious defects in the design before sending it to OPC, with a Capture Ratio of over 90%.
Help improve manufacturability
In fact, DRC checking only tells a black-and-white conclusion of whether there is a violation or not. It is impossible to know how much impact a certain degree of violation will have on the process side. PanGen DMC® can present the impact to users in a very visual way based on the model, helping users to weigh the violation handling according to the situation in practice. Therefore, whether for the manufacturing side or the design side, this product can be used as a very powerful supplement to the existing DRC (Design Rule Check) tool. On the basis of respecting the customer's existing workflow, it helps customers to more comprehensively discover the risks of the layout in process manufacturability in addition to DRC checking, thereby accelerating iterations, reducing time costs, and enabling new chip products to increase yield faster during the tape-out process and be brought to market earlier.
Comprehensive and forward-looking computational lithography platform PanGen ®
So far, Oriental Crystal Source's computational lithography platform PanGen® has formed eight major product matrices, including Model, DRC, SBAR, OPC, LRC, DPT, SMO, and DMC, with a complete computational lithography-related EDA tool chain. In addition, the PanGen® platform not only has OPC optimization functions suitable for mature process nodes, but is also the first mask optimization tool with full-chip reverse lithography (ILT) functions with a CPU+GPU hybrid computing architecture, and has key technologies for application in advanced process nodes. The research and development and verification of PanGen DMC® will further consolidate Oriental Crystal Source's technical integrity and leadership in the field of computational lithography, and bring more comprehensive and forward-looking computational lithography solutions to the industry.