Chinese semiconductor thread II
- Thread starter vincent
- Start date
That's what I like about the Chinese system, the competition within, Shanghai vs Beijing, While Shanghai SMIC is ahead due to ASML had an established base in the city, Beijing will not be outdone by investing in SMIC FAB plant using mostly indigenous equipment. Now that rivalry had spill over to EUVL power source with Beijing SSMB and Shanghai FEL.
Agree!!! with the same timeframe
WS10 - SMEE 28NM DUVL prototype
WS10A/B - SMEE SSA800A
WS10C - SMEE SSA900A
WS15 - EUVL prototype
WS15A - SSA1000 EUVL
And both were born under the 02 Special Project .
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Xinlian Integrated Circuit's "epitaxial equipment" patent is authorized
Tianyancha shows that Xinlian Integrated Circuit Manufacturing Co., Ltd. recently obtained a patent called "epitaxial equipment", the authorization announcement number is CN221663071U, the authorization announcement date is September 6, 2024, and the application date is January 25, 2024.
Tianyancha shows that Xinlian Integrated Circuit Manufacturing Co., Ltd. recently obtained a patent called "epitaxial equipment", the authorization announcement number is CN221663071U, the authorization announcement date is September 6, 2024, and the application date is January 25, 2024.
Some of Huawei's solutions and trends in the semiconductor field:
1. Transistors can adopt a gate-all-around (GAA) structure, that is, the gate surrounds the channel. The gate-all-around structure improves the control ability of the gate by controlling the channel electric field in all directions, greatly reducing the short channel effect, so that the gate length can be reduced to 5nm or even smaller without basically affecting the performance. This design enhances the regulation of electrons in the channel, avoids the gate controlling the channel from only a single direction, and solves the problem of poor control of planar transistors at small sizes. Currently, Samsung has introduced a GAA structure in its 3nm process, called MBCFET; TSMC will introduce a GAA structure in its future 2nm process.
2. Nanotube disordered mesh films can be used instead of traditional silicon-based channel materials. Carbon nanotubes (CNTs) as channel materials have better electrical properties, especially at extremely small sizes (such as below 5nm), their carrier mobility is much higher than silicon. In addition, the nanotubes are arranged in a disordered mesh structure, which simplifies the process flow and avoids complex crystal alignment processes. The structure has good matching with the ring gate structure, which enables each nanotube to have uniform gate control capabilities and avoid local performance differences.
3. A multi-layer channel design can be adopted. The transistor includes a vertically stacked multi-layer channel structure, and each layer of the channel is separated by an independent gate. In this way, by increasing the number of channel layers in the vertical direction, the current density of the device can be effectively increased, and the on-state current and overall performance can be improved. In addition, each layer of the channel is separated by a gate to ensure that each channel can be uniformly and independently controlled, avoiding the interference effect that may occur when the channel is stacked in a traditional planar transistor.
4. High-k dielectrics (such as hafnium oxide) are used as gate dielectrics. Compared with traditional dielectric materials such as silicon dioxide, high-k dielectric materials have a higher dielectric constant (k value), which can improve the electric field control capability of the gate, thereby maintaining better electrical performance under smaller gate length conditions. This solution has been implemented in 7nm chips and has been widely adopted in the industry.
5. The gate can be made directly from palladium metal materials. Palladium metal has high chemical stability and good conductivity. As a gate material, it can simplify the manufacturing process and reduce the multiple process steps involved in traditional semiconductor processes. Currently, the industry mainly uses metal materials such as titanium and cobalt.
Source:
1. Transistors can adopt a gate-all-around (GAA) structure, that is, the gate surrounds the channel. The gate-all-around structure improves the control ability of the gate by controlling the channel electric field in all directions, greatly reducing the short channel effect, so that the gate length can be reduced to 5nm or even smaller without basically affecting the performance. This design enhances the regulation of electrons in the channel, avoids the gate controlling the channel from only a single direction, and solves the problem of poor control of planar transistors at small sizes. Currently, Samsung has introduced a GAA structure in its 3nm process, called MBCFET; TSMC will introduce a GAA structure in its future 2nm process.
2. Nanotube disordered mesh films can be used instead of traditional silicon-based channel materials. Carbon nanotubes (CNTs) as channel materials have better electrical properties, especially at extremely small sizes (such as below 5nm), their carrier mobility is much higher than silicon. In addition, the nanotubes are arranged in a disordered mesh structure, which simplifies the process flow and avoids complex crystal alignment processes. The structure has good matching with the ring gate structure, which enables each nanotube to have uniform gate control capabilities and avoid local performance differences.
3. A multi-layer channel design can be adopted. The transistor includes a vertically stacked multi-layer channel structure, and each layer of the channel is separated by an independent gate. In this way, by increasing the number of channel layers in the vertical direction, the current density of the device can be effectively increased, and the on-state current and overall performance can be improved. In addition, each layer of the channel is separated by a gate to ensure that each channel can be uniformly and independently controlled, avoiding the interference effect that may occur when the channel is stacked in a traditional planar transistor.
4. High-k dielectrics (such as hafnium oxide) are used as gate dielectrics. Compared with traditional dielectric materials such as silicon dioxide, high-k dielectric materials have a higher dielectric constant (k value), which can improve the electric field control capability of the gate, thereby maintaining better electrical performance under smaller gate length conditions. This solution has been implemented in 7nm chips and has been widely adopted in the industry.
5. The gate can be made directly from palladium metal materials. Palladium metal has high chemical stability and good conductivity. As a gate material, it can simplify the manufacturing process and reduce the multiple process steps involved in traditional semiconductor processes. Currently, the industry mainly uses metal materials such as titanium and cobalt.
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Agreed. Too much conjecture. Here is my lastest post on the China market (remember my articles now are on Substack, not Seeking Alpha. According to my article, the only appreciable semiconductor equipment market will be in China. Read it here:
WFE Analysis For 2024: Sell Side Analysts Are Slowly Agreeing With Me
keep in mind that @tinrobert relies on subscription to earn a living. The link he was providing was the deep dive, which requires a subscription.
What you posted is fine, since it's directly from his substack, but please don't take content from his paid section and put it on pastebin or something like that.