Chinese semiconductor thread II

tokenanalyst

Brigadier
Registered Member
Do you guys ever wonder if State Department stooges are in this thread right now mining it for intel?
I guess some think tankers scout this thread for information but they are too ashamed of admitting that in public giving the pro-Chinese stance of this forum because the heaven forbid that you say anything positive about China in the internet and/or point out the bullshit.

In my opinion the stooges in the W.H are just too far gone ideologically to even process the information that we post here. Sullivan said the other day "US curbs are working no matter what Beijing says.", this people don't care if US companies lose 40% of their revenue overnight, big job losses and cuts in R&D spending. They see US semiconductors industry concerns of total destruction as "unpatriotic". The same people who wasted 20 yeas in Afghanistan to achieve nothing.

The thing is that Beijing is not saying nothing, this is only the evidence that this sanctions and export controls on China are accelerating what was stagnant for decades due US companies monopolization of China IT-semiconductor-electronics industry. The information we post here is just the tip of the iceberg, probably no even close to 30% of the development happening in China. They are obfuscating a lot development of their semiconductor industry, is becoming like a semiconductor black box as China become more independent and with a reason.
 

OptimusLion

New Member
Registered Member
CIOE2024 Shenzhen Optical Expo concluded successfully, and Zhongke Guangzhi brought its new chip placement machine products to a wonderful appearance

From September 11 to 13, 2024, the 3-day 25th China International Optoelectronics Expo was successfully held and successfully concluded. The scale of this exhibition was unprecedentedly grand, attracting more than 3,700 high-quality optoelectronic companies from around the world to gather together. Many professionals went to the scene to exchange and discuss, lighting up the wisdom spark of the development of the global optoelectronics industry. #Zhongke Guangzhi# will be unveiled at booth 10A39 in Hall 10-Semiconductor and Optical Communication Intelligent Equipment Hall.
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european_guy

Junior Member
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I have checked the link and now they have changed the text!

Now they acknowledge the new memory is done with Chinese equipment, as is the most natural explanation for shrinking from 232 to 160 layers, as many have pointed out.

What is interesting is that now we have for the first time a quantitative performance difference on NAND manufacturing between LAM Research and AMEC etcher:

US LAM etcher's 232 layers vs Chinese AMEC's 160 layers and 155nm pitch

So future steps will be 160 -> 192 -> 232. How much time it will take? Difficult to say, very probably next iteration, possibly next year, will be at least 192 layers.

But what it means in practice 232 vs 160? It means that for the same cost, NAND memory has 31% less capacity. If next year they go to 192 layers, they will reduce the gap to 17%.

Regarding 512 Gb die size of 40.44 mm², assuming is 6.4 X 6.32mm -> 1509 dies per 300mm wafer.

Assuming a conservative yield of 70% -> 67.6TB per wafer -> 132 phones per wafer (512GB each)

So 10M phones need 76K wafer (with yield 70%)

Finally, leaving numbers aside, the most sensible point of this important news is that we have confirmation YMTC successfully de-americanized their production line!
 
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huemens

Junior Member
Registered Member
But what it means in practice 232 vs 160? It means that for the same cost, NAND memory has 31% less capacity. If next year they go to 192 layers, they will reduce the gap to 17%.
YMTC 232L (Xtacking 3.0) density is 15.03 GB/mm2, Micron 232L is 14.6GB/mm2. Xtacking 4.0 with 160L density is 12.66GB/mm2. So the capacity drop in the current iteration, per die area, in comparison to YMTC 232L is only 16% (achieved with 31% fewer layers) and in comparison to Micron 232L is 13%. So if they are able to scale the current process to 192 layers it would surpass the Xtacking 3.0 232L in terms of capacity.
 
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antiterror13

Brigadier
YMTC 232L (Xtacking 3.0) density is 15.03 GB/mm2, Micron 232L is 14.6GB/mm2. Xtacking 4.0 with 160L density is 12.66GB/mm2. So the capacity drop in the current iteration, per die area, in comparison to YMTC 232L is only 16% and in comparison to Micron 232L is 13%.

not bad huhhh :)
 

Quickie

Colonel
YMTC 232L (Xtacking 3.0) density is 15.03 GB/mm2, Micron 232L is 14.6GB/mm2. Xtacking 4.0 with 160L density is 12.66GB/mm2. So the capacity drop in the current iteration, per die area, in comparison to YMTC 232L is only 16% (achieved with 31% fewer layers) and in comparison to Micron 232L is 13%. So if they are able to scale the current process to 192 layers it would surpass the Xtacking 3.0 232L in terms of capacity.

With half the number of layers, that should also come with significant power consumption savings.
 

huemens

Junior Member
Registered Member
With half the number of layers, that should also come with significant power consumption savings.

Power consumption is lower than previous gen, but not because of the number of layers. It is due to enhancements to the architecture. If there are fewer layers they have to compensate that with die area to get a certain number of bits per chip.
From TechInsights:
  1. Centered X-DEC die design: This architectural enhancement improves read/write performance by reducing wordline (WL) capacitance and RC load, cutting WL settling time and current demands.
  2. Backside Source Connect (BSSC): First used in Xtacking3.0, BSSC helps streamline vertical connections, now applied to the 160-layer TLC chip for enhanced performance.
  3. Vertical channel (VC) design: The 20-hole VC design, shared with KIOXIA’s BiCS8 218L, eliminates dummy holes, optimizing the 155 nm pitch for better cell density and efficiency.
  4. Higher bit density and reduced die size: With a die size of 40.44 mm² and a density of 12.66 Gb/mm² for the 512 Gb chip, Xtacking4.0 offers increased storage capacity and performance within a smaller footprint.
  5. Hybrid bonding maturity: This technology, crucial to YMTC’s process, is now more refined and is the backbone of YMTC’s high-density, vertically connected 3D NAND chips.
 
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