When is YMTC projected to go back to 232 layers?
I have checked the link and now they have changed the text!
Now they acknowledge the new memory is done with Chinese equipment, as is the most natural explanation for shrinking from 232 to 160 layers, as many have pointed out.
What is interesting is that now we have for the first time a quantitative performance difference on NAND manufacturing between LAM Research and AMEC etcher:
US LAM etcher's 232 layers vs Chinese AMEC's 160 layers and 155nm pitch
So future steps will be 160 -> 192 -> 232. How much time it will take? Difficult to say, very probably next iteration, possibly next year, will be at least 192 layers.
But what it means in practice 232 vs 160? It means that for the same cost, NAND memory has 31% less capacity. If next year they go to 192 layers, they will reduce the gap to 17%.
Regarding 512 Gb die size of 40.44 mm², assuming is 6.4 X 6.32mm -> 1509 dies per 300mm wafer.
Assuming a conservative yield of 70% -> 67.6TB per wafer -> 132 phones per wafer (512GB each)
So 10M phones need 76K wafer (with yield 70%)
Finally, leaving numbers aside, the most sensible point of this important news is that we have confirmation YMTC successfully de-americanized their production line!
Any links to this 160 layer version? Aliexpress etc?
Do you guys ever wonder if State Department stooges are in this thread right now mining it for intel?
why such pessimism? 2023, they said their tools can be used to resume YMTC production at 128 layers. A year later, they already increased it to 160 layers.Until AMEC can make proper toll to make 232 layers, my guess is in 2026 and at time YMTC may have Xtacking 6.0 technology
Power consumption is lower than previous gen, but not because of the number of layers. It is due to enhancements to the architecture. If there are fewer layers they have to compensate that with die area to get a certain number of bits per chip.
From TechInsights:
the latter is more of a concern for YMTC than Huawei. Fewer chips per wafer and high capex in recent years just mean YMTC probably can't make good margins for a few years. That's no big deal really. 16% less dense is really not that bad tbh.YMTC 232L (Xtacking 3.0) density is 15.03 GB/mm2, Micron 232L is 14.6GB/mm2. Xtacking 4.0 with 160L density is 12.66GB/mm2. So the capacity drop in the current iteration, per die area, in comparison to YMTC 232L is only 16% (achieved with 31% fewer layers) and in comparison to Micron 232L is 13%. So if they are able to scale the current process to 192 layers it would surpass the Xtacking 3.0 232L in terms of capacity.
If I was to guess, it's probably a one generation change. AMEC shouldn't need an interim step that only increases ratio by 20%.
Also capacity part is probably not true, because the article itself stated that the bit-density of this Xtacking 4.0 is competitive with 232 layers from competition. So, it's quite likely that Xtacking 4.0 just allows greater density for its number of layers.
I'm not too sure about the math part of this. Did the article say 512 Gb die has size of 40.44 mm2?
Perhaps the better word is realistic .... 160 layers in 2024, 192 layers in 2025 and 223 layers in 2026why such pessimism? 2023, they said their tools can be used to resume YMTC production at 128 layers. A year later, they already increased it to 160 layers.
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