Chinese semiconductor thread II

[tokenanalyst]

Semiconductor device and manufacturing method thereof​

IMECAS
CN117913122A

Abstract​

The application provides a semiconductor device and a method for manufacturing the same, the semiconductor device includes: the source electrode, the drain electrode, the grid electrode and the channel structure are arranged on one side of the substrate, the channel structure comprises a lamination formed by a plurality of nano sheets, and the grid electrode surrounds the nano sheets. In the present application, the substrate may include a first substrate and a second substrate which are sequentially stacked, wherein the first substrate is a semiconductor material and the second substrate is an insulating material, that is, the substrate of the present application is a semiconductor-on-insulator substrate, so that the performance of GAAFET can be optimized. The semiconductor device provided by the application comprises the isolation structure, wherein the isolation structure is arranged between the channel structure and the second substrate, and extends to the source electrode and the drain electrode in the direction parallel to the plane of the substrate, so that effective isolation is formed among the substrate, the grid electrode, the drain electrode and the source electrode, and parasitic channel leakage of the substrate is restrained by utilizing the isolation structure, thereby reducing off-state leakage current of the device under the condition of shorter grid length and improving the integral performance of the device.​

 

[jli88]

I think that was a quote from a Taiwanese publication. I don't know what it is, but lately they have this nasty habit of putting words in other people mouths, like if they are desperate for something.

The reality is that nobody knows, China semiconductor industry is a black box now. I don't think there is nothing stopping Huawei and SMIC from reaching 5nm, if TSMC didn't have EUV they will still making chips using DUVi, using SAQP or another patterning techniques. Back at 2022 everybody including a lot of experts inside China where hell bent that was impossible for SMIC and Huawei to make 7nm chips in volume, they demonstrated the contrary, a win for multiple patterning techniques. I myself was expecting that it would take them a lot longer to reach 7nm in volume and they surprise me.

The quotes are correct. Reported here as well:

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Anyways, we will see shortly, The consensus on this forum is that there will be a 5 nm (or 5.5 nm) chip by Huawei in the upcoming phone this fall. Let's see.

 

[siegecrossbow]

On May 30, Huawei Managing Director and Huawei Cloud CEO Zhang Ping'an attended the China Mobile Computing Conference and told industry colleagues: "We definitely can't get 3nm, we can't get 5nm, “It would be great if we could solve 7 nanometers,” he admitted. ”

Zhang Ping'an said that due to the dilemma of the chip manufacturing process, the direction of innovation can no longer rely on single-point chip processing, but can only rely on system architecture innovation. For domestic chip manufacturers, it will be difficult to produce chips below 7nm for a long time to come.

Has Huawei failed to mass produce 5 nanometers?

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You are quoting FLG source.

 

[tokenanalyst]

The quotes are correct. Reported here as well:

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Anyways, we will see shortly, The consensus on this forum is that there will be a 5 nm (or 5.5 nm) chip by Huawei in the upcoming phone this fall. Let's see.

I was reading he was referring to the fact they wont get 3nm or 5nm chips from TSMC, as now the only thing they have is SMIC 7nm, again the context is missing here.
And is no only in this forum, EUV cut the number of layers but is not an impediment to reach 5nm or even 3nm, DUVi can definitely get there using self-alignment, multiple patterning with good overlay metrology, or even self assembly techninques, in fact have been reading that there is a posibility that ASML may have oversold the benefits of EUV and instead of fabs focusing in cheaper solutions now fabs are stuck with a technology that is eating the fab, half of a fab costs now are lithography more than with DUVi and those cost has to be passed to the consumers, the fact the Intel decided to adopt HiNA EUV before LowNA EUV even matured is pretty suspicious.
And one the things these guys are trying to say in their own ways is that Huawei may prove that EUV was adopted too early and that there are more cheaper techniques the weren't explored before adopting EUV but in the other hand EUV is still new and probably as mature become more cheaper and easier, who knows and Huawei achieving 3nm still remain to be see.

 

[lcloo]

"We definitely can't get 3nm, we can't get 5nm, “It would be great if we could solve 7 nanometers,” he admitted. ”

“我们肯定是得不到 3nm，肯定得不到 5nm，我们能解决 7nm 就非常非常好。”
We certainly cannot get 3nm, and certainly not 5nm, it's very good that we can solved 7nm (problem).

1) "definitely cannot get 3nm, 5nm" = cannot purchase 3nm, 5nm (from Taiwan, US). It is not the same as we cannot produce 3nm. 5nm in China in future.

2) "We definitely can't get 3nm, we can't get 5nm, “It would be great if we could solve 7 nanometers,” he admitted. ” is not the same as " it's very good that we can solved 7nm (problem).". Fact: Pura 70.

Correct interpretation is important. We may see Huawei 5nm chip before end of this year.

 

[Hyper]

I was reading he was referring to the fact they wont get 3nm or 5nm chips from TSMC, as now the only thing they have is SMIC 7nm, again the context is missing here.
And is no only in this forum, EUV cut the number of layers but is not an impediment to reach 5nm or even 3nm, DUVi can definitely get there using self-alignment, multiple patterning with good overlay metrology, or even self assembly techninques, in fact have been reading that there is a posibility that ASML may have oversold the benefits of EUV and instead of fabs focusing in cheaper solutions now fabs are stuck with a technology that is eating the fab, half of a fab costs now are lithography more than with DUVi and those cost has to be passed to the consumers, the fact the Intel decided to adopt HiNA EUV before LowNA EUV even matured is pretty suspicious.
And one the things these guys are trying to say in their own ways is that Huawei may prove that EUV was adopted too early and that there are more cheaper techniques the weren't explored before adopting EUV but in the other hand EUV is still new and probably as mature become more cheaper and easier, who knows and Huawei achieving 3nm still remain to be see.

Okay so the history of euv adoption goes like this. Intel 10nm was a very ambitious node and they tried SAQP or even Octa patterning in 1 or 2 critical layers. Tsmc had much more relaxed node design. N7 and N7E was a duv node on NXT:2000i. N6 and N7P introduced euv to high volume manufacturing. N5 was the first proper node that used EUV. However ASML released two new duv scanners after 2000i, namely NXT:2050i and NXT:2100i, which should enable 5nm with duv. TSMC did not use duv because they already had EUV. As such EUV has a whole new set of problem which still remain unsolved. The photons are too energetic, resists are not well developed, masks are not well developed ( lack damage resistance). EUV is a necessary evil for the industry. So from 2035 onwards lithography enabled scaling will be dead and CFET and TMD will enable scaling.

 

[tonyget]

"We definitely can't get 3nm, we can't get 5nm, “It would be great if we could solve 7 nanometers,” he admitted. ”

“我们肯定是得不到 3nm，肯定得不到 5nm，我们能解决 7nm 就非常非常好。”
We certainly cannot get 3nm, and certainly not 5nm, it's very good that we can solved 7nm (problem).

1) "definitely cannot get 3nm, 5nm" = cannot purchase 3nm, 5nm (from Taiwan, US). It is not the same as we cannot produce 3nm. 5nm in China in future.

2) "We definitely can't get 3nm, we can't get 5nm, “It would be great if we could solve 7 nanometers,” he admitted. ” is not the same as " it's very good that we can solved 7nm (problem).". Fact: Pura 70.

Correct interpretation is important. We may see Huawei 5nm chip before end of this year.

I don't think that is the correct interpretation. Because Huawei cannot get ANYTHING from TSMC now，so if what he wants is to stress what Huawei can purchase from TSMC，he would have say that they cannot buy anything from TSMC.

 

[Phead128]

I don't think that is the correct interpretation. Because Huawei cannot get ANYTHING from TSMC now，so if what he wants is to stress what Huawei can purchase from TSMC，he would have say that they cannot buy anything from TSMC.

If you listen the video, he describes 3nm and 5nm in detail in his speech leading up to the quoted snippets. It makes no sense in the context to make a blanket no purchase anything, it fits perfectly well for him to individually call out 3nm and 5nm given the context of his speech. You can't take quoted snippets in isolation outside the context of his speech.

 

[Hyper]

I don't think that is the correct interpretation. Because Huawei cannot get ANYTHING from TSMC now，so if what he wants is to stress what Huawei can purchase from TSMC，he would have say that they cannot buy anything from TSMC.

They might have delayed their projects. Also a possibility is that they might have run into problems with 5nm. Westlake paper was released in March. No chance it can be implemented so quickly.

 

[aptmind]

Semiwiki states that DUV SAQP means that such a process restricts design flexibility so the node is probably tailore made for Huawei. 90% of the wafers are for Huawei.

This just isn't true, although the overall argument is sound. The foundry and SOC designer work closely on developing an optimal mixture of high density and high performance libraries of standard designs.

This is why most SOCs do not hit the theoretical density values that foundries publish for hype. Ultra high density and high density libraries are actually relatively uncommon in most modern SOCs.

Suffice to say, the foundry does not design an entire node class for a single customer. Apple didn't convince TSMC to make 3NB for them (turned out to be a dud after all), TSMC pursued that independently with the understanding that Apple would be a highly likely customer. Foundries design the best node to balance performance, yield, and cost. Then they offer a number of libraries, which the SOC designer then can provide feedback on and "self-design" from there. Trying to change the libraries outside of very minor edits would be a very time-consuming issue since large changes would potentially harm yield (and the machines) if outside optimal specs.