The Institute of Metal Research, Chinese Academy of Sciences, has made important breakthroughs in the research of two-dimensional semiconductor devices
Information from the Institute of Metal Research, Chinese Academy of Sciences shows that under the leadership of Professor Han Zheng of Shanxi University, a collaboration involving Researcher Li Xiuyan from the Institute of Metal Research, Chinese Academy of Sciences, Associate Researcher Wang Hanwen from Liaoning Materials Laboratory, Professor Hou Yanglong from Sun Yat-sen University, and Professor Zhou Wu from University of Chinese Academy of Sciences has proposed a new p-doped two-dimensional semiconductor method based on interface coupling (theory shows that quantum effects play a key role in this), providing ideas for the development of future two-dimensional semiconductor devices in the post-Moore era.
As semiconductor process technology continues to approach the sub-nanometer physical limit, developing a vertically structured multi-layer interconnected CMOS logic circuit to achieve a breakthrough in three-dimensional integration technology is one of the new paths actively explored in the international semiconductor field. Since the silicon-based transistor preparation process uses ion implantation on the surface of single-crystal silicon, it is difficult to grow or transfer single-crystal silicon again on top of a layer of ion-implanted single-crystal silicon. Although the integration level can be improved by connecting electrodes and core particles in three-dimensional space, the key transistors are always distributed at the bottom layer and cannot obtain the degree of freedom in the z direction. New materials or disruptive principles have therefore become important breakthroughs that have attracted much attention.
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Here's the paper for anyone interested.
Van der Waals polarity-engineered 3D integration of 2D complementary logic
Abstract
Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the
z axis
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. Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures
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, as well as hetero-2D layers with different carrier types
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, have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe2 (refs.
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) and MoS2 (refs.
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)) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS2, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS2 can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm2 V−1 s−1, on/off ratios reaching 106 and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.
