Chinese semiconductor thread II

nativechicken

Junior Member
Registered Member
It depends on the steps. If it didn’t TSMC wouldn’t use EUV at all. There are critical steps where DUVi has insufficient resolution even if there’s noise issues with EUV, and for those EUV is not only preferred but nonnegotiable.
Yes, the source spent over ten to twenty minutes specifically addressing these two points you raised. For the domestic DUVi systems, a dedicated solution was implemented—reportedly mobilizing thousands of researchers who conducted massive mathematical studies and simulations on every microscopic detail of the production process. Only after confirming optimal equipment parameters and investing substantial resources did they achieve breakthroughs for entirely new DUVi systems and production processes.

Producing 5nm chips on DUVi equipment would be simply impossible with ASML’s standard systems.

The true cost lies in the yield rate sacrifices and extended tape-out cycles—with overall production time significantly increasing as process complexity intensifies.
 

nativechicken

Junior Member
Registered Member
you are not stating anything that is not obvious so I would say that you should stop talking like that.

as for your stuff about tuning and process and such, that is kind of not relevant. As I said earlier, they absolutely do not need to wait until they are confirmed and yield is at a certain point before starting serial production using EUV. Since any EUV process for 5nm is pretty much better than a DUVi process. As such, saying EUV right now is where DUVi was at 2021 is entirely meaningless since their domestic machine doesn’t have to compete against ASML EUV.

I have in fact heard about anything from risk production later this year to serial production in 2028. Depending on what customer is willing to live with in terms of cost or yield/consistency, any number of years in between is reasonable.
What I’ve heard is that current 5nm production relies on modified ASML machines combined with domestic DUVi systems—specifically using quadruple patterning alignment technology.

While the EUV hardware is ready, it lacks mature supporting infrastructure. Solutions for metrology tools, photoresists, and ancillary components exist but remain unoptimized. Crucially, EUV process parameter libraries are being built from zero—doping parameters for EUV-compatible ion implantation/deposition, photoresist tuning coefficients, etc.—all require foundational development.

The system functions unstably. Every component is undergoing calibration, making immediate production line deployment impractical. This 1.5-2 year stabilization phase is unavoidable before pilot production can begin.

Though I too hope domestic EUV accelerates, current evidence makes his timeline credible. Personally, I’ve tracked semiconductor lithography literature for over a decade (albeit as an observer without operational experience). His 4-hour presentation—including ~90 minutes of chip fabrication analysis—demonstrates striking coherence with my technical understanding. His breakdown of inherent sub-7nm noise issues (citing three distinct noise sources) aligns with my accumulated knowledge and even deepened my perspective on certain details.

While he isn’t a semiconductor industry insider, his access is verified:

Engages directly with China’s semiconductor leadership
Attended at least one of six classified strategy meetings that reshaped China’s post-trade-war semiconductor response (2018-2022)
Thus, I find his analysis substantiated.
 
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Hyper

Junior Member
Registered Member
Based on what I've heard, current 5nm production utilizes modified ASML machines alongside domestic DUVi systems—specifically through quadruple patterning alignment technology.

While the EUV hardware exists, full implementation requires supporting infrastructure. Solutions for metrology tools, photoresists, and other ancillaries exist but remain immature. Critically, EUV process libraries are being built from scratch: doping parameters for EUV-enabled ion implantation/deposition, photoresist tuning parameters, etc.

The current ecosystem operates but lacks stability—every component requires optimization. Direct production line deployment isn't viable yet. A 1.5-2 year maturation period is unavoidable before pilot production can commence.

Though I too wish domestic EUV could accelerate, based on available information, the presenter’s timeline appears credible. With over a decade tracking microelectronics/lithography literature (albeit as an observer, not practitioner), his four-hour video—including ~90 minutes dedicated to chip fabrication—contains granular technical coherence. His explanations of unavoidable sub-7nm noise issues (detailing three distinct noise sources) align with my accumulated understanding, even deepening certain technical insights.

Crucially, while not a semiconductor industry insider himself, he demonstrably accesses senior-level intelligence:

Maintains dialogue with China’s semiconductor leadership
Attended at least one of six pivotal closed-door meetings that reshaped China’s semiconductor strategy post-trade-war (2018-2022), granting unique perspective beyond public disclosures
Therefore, I find his analysis substantiated and persuasive.
Any links to video?
 

latenlazy

Brigadier
Based on what I've heard, current 5nm production utilizes modified ASML machines alongside domestic DUVi systems—specifically through quadruple patterning alignment technology.

While the EUV hardware exists, full implementation requires supporting infrastructure. Solutions for metrology tools, photoresists, and other ancillaries exist but remain immature. Critically, EUV process libraries are being built from scratch: doping parameters for EUV-enabled ion implantation/deposition, photoresist tuning parameters, etc.

The current ecosystem operates but lacks stability—every component requires optimization. Direct production line deployment isn't viable yet. A 1.5-2 year maturation period is unavoidable before pilot production can commence.

Though I too wish domestic EUV could accelerate, based on available information, the presenter’s timeline appears credible. With over a decade tracking microelectronics/lithography literature (albeit as an observer, not practitioner), his four-hour video—including ~90 minutes dedicated to chip fabrication—contains granular technical coherence. His explanations of unavoidable sub-7nm noise issues (detailing three distinct noise sources) align with my accumulated understanding, even deepening certain technical insights.

Crucially, while not a semiconductor industry insider himself, he demonstrably accesses senior-level intelligence:

Maintains dialogue with China’s semiconductor leadership
Attended at least one of six pivotal closed-door meetings that reshaped China’s semiconductor strategy post-trade-war (2018-2022), granting unique perspective beyond public disclosures
Therefore, I find his analysis substantiated and persuasive.
I think it can both be the case that the presenter’s understanding of all the optimization details that need to be done for effective mass employment are correct *and* that EUV is such a capability uplift for critical steps towards future node shrinks that even a suboptimal process will be employed as best they’re able to just to continue pushing an aggressive product cadence. If for example Huawei can get to 3 nm with an expensive EUV process that is inefficient and has some yield penalties faster than with sextuple patterning that is what they will do. They may even run batches employing two different processes just to hedge their bets and see which will get them to the next node shrink faster. The ideal “stable” industry wide employment of EUV can take another 1.5-2 years *and* EUV can potentially be employed for those who are willing to pay up on risk and costs as soon as any process is minimally viable.
 

nativechicken

Junior Member
Registered Member
Any links to video?
The video emphasized: don't circulate this widely, especially the video itself. Privately celebrate the information—but public sharing could complicate things for the presenter. Everything shared was cleared for discussion within appropriate circles.
Additionally, there were discrepancies between the earlier translation and my original intended meaning. The updated post has now corrected these specific sections.
 
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henrik

Senior Member
Registered Member
Basically a export tax. Nvidia will hide revenue and hide sales geography through accounting tricks. Sales will register in Taiwan and Singapore.

They have to cut prices before selling to China, otherwise they will not buy due to security concerns.
 

tphuang

General
Staff member
Super Moderator
VIP Professional
Registered Member
What I’ve heard is that current 5nm production relies on modified ASML machines combined with domestic DUVi systems—specifically using quadruple patterning alignment technology.

While the EUV hardware is ready, it lacks mature supporting infrastructure. Solutions for metrology tools, photoresists, and ancillary components exist but remain unoptimized. Crucially, EUV process parameter libraries are being built from zero—doping parameters for EUV-compatible ion implantation/deposition, photoresist tuning coefficients, etc.—all require foundational development.

The system functions unstably. Every component is undergoing calibration, making immediate production line deployment impractical. This 1.5-2 year stabilization phase is unavoidable before pilot production can begin.

Though I too hope domestic EUV accelerates, current evidence makes his timeline credible. Personally, I’ve tracked semiconductor lithography literature for over a decade (albeit as an observer without operational experience). His 4-hour presentation—including ~90 minutes of chip fabrication analysis—demonstrates striking coherence with my technical understanding. His breakdown of inherent sub-7nm noise issues (citing three distinct noise sources) aligns with my accumulated knowledge and even deepened my perspective on certain details.

While he isn’t a semiconductor industry insider, his access is verified:

Engages directly with China’s semiconductor leadership
Attended at least one of six classified strategy meetings that reshaped China’s post-trade-war semiconductor response (2018-2022)
Thus, I find his analysis substantiated.
Right, I think it’s great that you have now explained what his background is. I think his info is very useful but there are also multiple parties working on EUV systems in China. Depending on their requirements, they may have tolerance for more or less stable production using EUV. In fact, DUVi 7nm process is also not that stable. Hence you saw the pitch only change from 42nm in 2023 to 40nm last year iirc. It takes 3 to 6 months for each batch of chips to be produced so it really takes time to improve their process, especially when they had limited number of suitable equipment. Going from 40nm to 36nm will take additional effort that is likely to take time to become stable also.

again, that’s why @latenlazy and I think they are going to tolerate instability in EUV for the critical step. It’s because the process using DUVi using multi patterning is itself lower yield and take long time to stabilize.
 

leibowitz

Junior Member
What I’ve heard is that current 5nm production relies on modified ASML machines combined with domestic DUVi systems—specifically using quadruple patterning alignment technology.

While the EUV hardware is ready, it lacks mature supporting infrastructure. Solutions for metrology tools, photoresists, and ancillary components exist but remain unoptimized. Crucially, EUV process parameter libraries are being built from zero—doping parameters for EUV-compatible ion implantation/deposition, photoresist tuning coefficients, etc.—all require foundational development.

The system functions unstably. Every component is undergoing calibration, making immediate production line deployment impractical. This 1.5-2 year stabilization phase is unavoidable before pilot production can begin.

Though I too hope domestic EUV accelerates, current evidence makes his timeline credible. Personally, I’ve tracked semiconductor lithography literature for over a decade (albeit as an observer without operational experience). His 4-hour presentation—including ~90 minutes of chip fabrication analysis—demonstrates striking coherence with my technical understanding. His breakdown of inherent sub-7nm noise issues (citing three distinct noise sources) aligns with my accumulated knowledge and even deepened my perspective on certain details.

While he isn’t a semiconductor industry insider, his access is verified:

Engages directly with China’s semiconductor leadership
Attended at least one of six classified strategy meetings that reshaped China’s post-trade-war semiconductor response (2018-2022)
Thus, I find his analysis substantiated.
Lmao this reads like AI slop. So many em dashes. And who is the "he" you are referencing and where is "his 4-hour presentation"
 
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