ZS Tech achieved mass production of 2 inch single crystal diamond wafers and diamond cooling layers. They also make jewelry level diamonds
2 inch single crystal diamond substrate by Ir/sapphire heterogeneous epitaxy
Chinese semiconductor thread II
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ZS Tech achieved mass production of 2 inch single crystal diamond wafers and diamond cooling layers. They also make jewelry level diamonds
2 inch single crystal diamond substrate by Ir/sapphire heterogeneous epitaxy
You misunderstand! I'm talking about lobbying in the EU by EU firms that have hypothetically purchased licenses for Chinese semi designs from fabless Chinese firms like Moore Threads or Cambricon Technologies, and then sell the resultant products to the Chinese market.
For example, sale restrictions placed on Nvidia are made only by the US government because Nvidia is a US corporation. An EU company is not subject to the sales restrictions that apply to US corporations. Nor can the US legislate laws to regulate EU companies especially if they don't engage in commerce in the US.
Gaoyu Electronics will build a production base for third-generation semiconductor reliability testing equipment
According to Chao News, the third-generation semiconductor reliability testing equipment production base project of Hangzhou Gaoyu Electronic Technology Co., Ltd. (hereinafter referred to as "Gaoyu Electronic") was signed and implemented in Xihu District, Hangzhou on February 14.
It is reported that the project is expected to achieve revenue of more than 750 million yuan in the next three years .
Gaoyu Electronics was established on October 16, 2009 with a registered capital of RMB 52.5 million. It is a leading domestic integrator of electronic component reliability test equipment, test equipment development and component reliability overall solution. The company's products are widely used in the national defense electronics industry and well-known domestic and foreign semiconductor companies.
In April 2024, Gaoyu Electronics' SiC MOSFET power cycle aging test system has been recognized as a "Zhejiang Provincial Scientific and Technological Achievement" by the Zhejiang Provincial Department of Science and Technology.
Anyone still caught pants down not one, not two, but half a decade after the start of the tech war sorta deserves to get pummeled. Just saying…
AMEC invested RMB 100 million to establish AMEC (Sichuan) Co., Ltd., holding 100% of the shares.
According to the information, China Micro Semiconductor Equipment (Sichuan) Co., Ltd. was established on February 25, 2025. The legal representative is Yin Zhiyao. The registered capital is 100 million yuan. The company is located in Chengdu. It is engaged in the manufacturing of special equipment for semiconductor devices, the sales of special equipment for semiconductor devices, technical services, technical development, technical consulting, technical exchanges, technology transfer, technology promotion, sales of special electronic equipment, manufacturing of special electronic equipment, manufacturing of semiconductor lighting devices, sales of semiconductor lighting devices, manufacturing of semiconductor discrete devices, sales of semiconductor discrete devices, manufacturing of electronic measuring instruments, sales of electronic measuring instruments, manufacturing of electronic components, manufacturing of electronic components and electromechanical components equipment, retail of electronic components, sales of electronic components and electromechanical components equipment, sales of optoelectronic devices, and other Other electronic device manufacturing, electronic product sales, electronic vacuum device sales, emerging energy technology research and development, environmental protection equipment manufacturing, environmental protection equipment sales, intelligent control system integration, software development, Internet of Things equipment sales, data processing services, information system integration services, information technology consulting services, goods import and export, technology import and export, smart home consumer equipment manufacturing, smart home consumer equipment sales, first-class medical device production, first-class medical device sales, second-class medical device sales, enterprise management, intellectual property services (except patent agency services), non-residential real estate leasing, property management, conference and exhibition services, social and economic consulting services, consulting and planning services, information consulting services (excluding licensed information consulting services), etiquette services.
Huawei Enjoy 70X will get upgraded soon, it will use Kirin-8000A SoC with 6 cores
Also supporting Beidou satellite photos
now frontal camera up to 32 megapixels.
They must have really lowered the cost of domestic supply chain.
8 GB DRAM & 256GB NAND is base option. So these must be really cheap
Panel-Level Packaging Will Enable Chiplet Packaging Advancements
The 3D packaging sector has been growing rapidly, driven by the expansion of chiplet packaging across the ecosystem. Chip and package sizes have also grown rapidly as 2 x 800mm2 chips are being placed in a single package along with high-bandwidth memory (HBM). Demand for these large chiplets has generated supply constraints due to how the chips are packaged – fan-out wafer level packaging (FOWLP) is currently the primary methodology.
To help resolve packaging supply chain constraints, the advanced and chiplet packaging industry is moving from round substrates to square panels. Wafer manufacturers and outsourced assembly and test (OSAT) suppliers have both proposed using square glass panel substrates to package large-area chiplets. This will significantly increase the number of chips that can be processed on a single panel.
Transitioning to panel-level packaging (PLP) has some additional advantages over WLP. For example, PLP enables the industry to significantly increase the substrate area for building chiplets and lowering packaging costs. The larger area allows more chips to be assembled in parallel, increasing capacity and thus helping to ease current supply constraints.
FOPLP will ease integrating various die technologies (e.g., logic, memory, and RF) into a single package, thus supporting more complex system designs. By utilizing fan-out techniques, designs can achieve the thinner profile and smaller footprint essential for modern consumer electronics. PLP integration can:
- Improve chiplet performance for the massive amounts of data being processed by artificial intelligence (AI), as well as in other compute-heavy applications;
- Assist with the implementation of HBM to help reduce compute times and power usage; and
- Allow for more efficient package device design, as opposed to the more typical board-level packaging approach.
Ultra C ECP ap-p Capabilities
At ACM Research, we have leveraged our deep-rooted expertise in wafer electrochemical plating (ECP) and copper processes for advanced packaging to develop the first commercial high-volume PLP copper deposition system targeting the large-panel market.
Our Ultra ECP ap-p tool will enable advanced FOPLP with submicron features on large panels, which are applicable for AI applications using large-chiplet graphics processing units (GPUs) and high-density HBM. The Ultra ECP ap-p can be used for plating steps in a variety of processes, including pillar, bump, and redistribution layer (RDL), as well as for fan-out and through-glass via (TGV) processes.
The system is designed to handle organic and glass substrates sized 510mm x 515mm and 600mm x 600mm, while effectively managing cover warpages up to 7mm. To achieve this, we’ve integrated innovative robot and chuck systems that give us a competitive advantage in this space. These advanced automation features enhance efficiency and quality control throughout the manufacturing process and adapt traditional wafer-processing steps for larger and heavier panels. Included are critical operations like panel flipping for correct orientation and face-down plating.
The tool has up to 16 plating chambers and can deposit copper, nickel, tin-silver, gold, and other plating materials. We developed the system with a unique chamber configuration that provides high plating efficiency with both excellent uniformity and no cross-contamination, which can be a problem for systems that handle the panels vertically. In addition, the multi-anode area distribution effectively controls the height of the edges and corners of the panel.
The newest addition to our family of Ultra ECP tools, the Ultra ECP ap-p offers the industry unique capabilities for PLP copper deposition. As FOPLP gains further momentum, we look forward to playing a significant role in enabling the technology’s advancement.
Our Ultra ECP ap-p tool will enable advanced FOPLP with submicron features on large panels, which are applicable for AI applications using large-chiplet graphics processing units (GPUs) and high-density HBM. The Ultra ECP ap-p can be used for plating steps in a variety of processes, including pillar, bump, and redistribution layer (RDL), as well as for fan-out and through-glass via (TGV) processes.
The system is designed to handle organic and glass substrates sized 510mm x 515mm and 600mm x 600mm, while effectively managing cover warpages up to 7mm. To achieve this, we’ve integrated innovative robot and chuck systems that give us a competitive advantage in this space. These advanced automation features enhance efficiency and quality control throughout the manufacturing process and adapt traditional wafer-processing steps for larger and heavier panels. Included are critical operations like panel flipping for correct orientation and face-down plating.
The tool has up to 16 plating chambers and can deposit copper, nickel, tin-silver, gold, and other plating materials. We developed the system with a unique chamber configuration that provides high plating efficiency with both excellent uniformity and no cross-contamination, which can be a problem for systems that handle the panels vertically. In addition, the multi-anode area distribution effectively controls the height of the edges and corners of the panel.
The newest addition to our family of Ultra ECP tools, the Ultra ECP ap-p offers the industry unique capabilities for PLP copper deposition. As FOPLP gains further momentum, we look forward to playing a significant role in enabling the technology’s advancement.
The world's first OLED under-screen camera notebook is released! TCL Huaxing × Lenovo.
Lenovo YOGA AIPC new product tasting conference, the YOGA Air X AI Yuanqi version notebook was released, which is the "world's first under-screen camera notebook".
The device has a 98% screen-to-body ratio and is equipped with a 14-inch 4K OLED display with a refresh rate of 120Hz. It is certified for Dolby Vision and DisplayHDR True Black 600 and covers 100% of the sRGB, P3, and Adobe RGB color gamuts.
EDA-Yield company Semitronix adopting DeepSeek and hopefully fine-tuning it for automating semiconductor related tasks.
Guangli Micro SemiMind platform connected to DeepSeek-R1, opening a new chapter in semiconductor intelligent R&D
AI Empowers Semiconductors to Create an Intelligent Future
With the rapid development of the semiconductor industry, technological innovation and intelligent transformation have become the core engines driving industrial upgrading. As a leading domestic supplier of integrated circuit EDA software and wafer-level electrical testing equipment, Guangli Micro has always been committed to breaking through industry bottlenecks with technology.
Recently, SemiMind, a semiconductor big model platform under Guangli Microelectronics, was officially connected to the DeepSeek-R1 big model. The deep collaboration allows SemiMind to better understand semiconductors.
- Accurate intent understanding: Natural language interaction is more in line with engineers' thinking, and complex needs can be responded to in seconds.
- Multimodal reasoning capability: Integrate multi-dimensional analysis of text, data, and charts to output highly credible conclusions.
SemiMind:The key to solving the semiconductor industry's transformation
As semiconductor manufacturing processes continue to advance, the industry faces three core challenges:
As semiconductor manufacturing processes continue to advance, the industry faces three core challenges:
- Data explosion: The amount of chip design and test data has increased dramatically, and traditional tools are inefficient in processing;
- R&D complexity increases: cross-link collaboration is difficult and highly dependent on manual experience;
- Talent and technology gap: It is difficult for small and medium-sized enterprises to reuse the experience of leading enterprises, and the cost of trial and error is high.
Based on more than 20 years of industry accumulation, Guangli Micro has launched the SemiMind semiconductor big model platform; an AI research and development base driven by " knowledge base + intelligent agent ", which aims to reconstruct the semiconductor R&D process through intelligentization, break the data silos, and achieve knowledge democratization and efficiency leap.
The SemiMind platform has completed deep integration with the INF-AI intelligent platform, supporting core functions such as intelligent question and answer, defect classification, automatic model analysis and optimization, and yield analysis. It is currently promoting docking with the DE-G platform (Guangliwei General Semiconductor Data Analysis Software) to achieve functions such as formula/code generation, automated data cleaning, complex data modeling, multi-dimensional visual analysis, and real-time predictive analysis.
For example, in the INF-AI platform, engineers often face complex requirements for multi-task operations, data analysis, and visualization, which are cumbersome to operate and highly customized. To this end, an intelligent workflow system is built based on large model technology, which can automatically parse engineers' natural language instructions and realize the process of "demand input-full process automated execution".
Huawei Mate 70 Pro Premium Edition running score appears on Geekbench6
Processor with a lower clock speed version of the Kirin 9020
Single core: 1450, Multi-core: 3793
Architecture: 1×2.40GHz + 3×2.00GHz + 4×1.60GHz
Processor with a lower clock speed version of the Kirin 9020
Single core: 1450, Multi-core: 3793
Architecture: 1×2.40GHz + 3×2.00GHz + 4×1.60GHz
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