Chinese semiconductor thread II

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tokenanalyst

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AMEC is working with CXMT to improve their DRAM etching process.
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Distortion Control when Etching DRAM Metal Contact​


Abstract:

Contact etch is a typical high-aspect-ratio etch, which highly requires less distortion at the bottom. We suspect that the non-uniform polymer deposition on the mask necking and the random charging on the side-wall will both result in distortion. The former mainly contributes to circularity. The later will cause the random direction at the bottom of hole. Based on the mechanism, we investigate some gases to improve the distortion by carbon mask modification and dielectric side-wall discharging.​

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latenlazy said:
Think it will continue to struggle with more complex patterns though.
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I don't think so, in fact because doesn't have to deal with the same light wave issues as optical lithography, it can pattern ANY imaginable pattern, nano patterns that would be impossible to make using conventional mask optical lithography techniques , is only limited by the template and that could be made using Direct writing techniques and cloned all over multiple templates.​

The bigger issues with NIL has been alignment, overlay, throughput and defectivity.
 
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latenlazy

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tokenanalyst said:
I don't think so, in fact because doesn't have to deal with the same light wave issues as optical lithography, it can pattern ANY imaginable pattern, nano patterns that would be impossible to make using conventional mask optical lithography techniques, is only limited by the template and that could be made using Direct writing techniques and cloned all over multiple templates.​

The bigger issues with NIL has been alignment, overlay, throughput and defectivity.
Click to expand...
I have to imagine though that the more complex the pattern the less forgiving your tolerance for overlay errors are and in a nano-print system any overlay error is at the wafer level not at the pattern detail level so it's just a much less forgiving workflow. That’s what I was getting at with struggling with more complex patterns.
 
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latenlazy said:
I have to imagine though that the more complex the pattern the less forgiving your tolerance for overlay errors are and in a nano-print system any overlay error is at the wafer level not at the pattern detail level so it's just a much less forgiving workflow.
Click to expand...
Overlay comes from stacking layer of patterns over layers of patterns, the error comes from the layers falling outside of design tolerance, I think you are referring to complex devices. The alignment issue in NIL comes because the pressing of the mold distort the wafer affecting overall overlay.

Either way because NIl doesn't suffer from aberrations, interference, diffractions can give much better resolution. If Canon solves the issue with defectivity, alignment, overlay and throughput. I could catapult NIL from being used in photonics and optics to full blown IC manufacturing, really cheap. And this Chinese NIL companies are watching and waiting to see what happen, because if Canon strike gold with their NIL tool companies like Tenren Nano will be showered in funding given the fact the Canon will not be allowed to export their tool to China.

But either way NIL along with EUV has been one of the technologies considered for the manufacturing of next gen MRAM by Nankai:
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"Obtained some representative work in key processes of micro-nano processing technology/ultra-precision manufacturing equipment and ultra-high density magnetic storage:

1) 7nm node extreme ultraviolet (EUV) lithography technology exposure agent research and development, 7nm Node/13nm period EUV interference lithography (IL) process, Si 3 N 4 mask manufacturing process for EUV/X-ray array technology;

2) Use EUVIL to prepare the smallest 20nm two-dimensional lattice that can be obtained by optical methods for the next generation of magnetic recording media;

3) 8/12-inch next-generation Sub-20nm spin transfer torque magnetic random access memory chip STT-MRAM process (comparable to the best Samsung process technology), 50nm resolution, 1:7.5, the world’s highest aspect ratio structure The 8/12 -inch nanoimprint equipment is used in the magnetic sensor array process;

4) Cooperate with GermanLitho/Tianren Micro-Nano Technology and Leuven Instrument industry-university-research institute to jointly develop special equipment focusing on magnetic sensor array/MRAM 2/4/6/8-inch nanoimprinting and 8/12-inch RIE/IBE dual engraving Etching technology exclusive etching equipment for magnetic materials."
 
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latenlazy

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tokenanalyst said:
Overlay comes from stacking layer of patterns over layers of patterns, the error comes from the layers falling outside of design tolerance, I think you are referring to complex devices. The alignment issue in NIL comes because the pressing of the mold distort the wafer affecting overall overlay.

Either way because NIl doesn't suffer from aberrations, interference, diffractions can give much better resolution. If Canon solves the issue with defectivity, alignment, overlay and throughput. I could catapult NIL from being used in photonics and optics to full blown IC manufacturing, really cheap. And this Chinese NIL companies are watching and waiting to see what happen, because if Canon strike gold with their NIL tool companies like Tenren Nano will be showered in funding given the fact the Canon will not be allowed to export their tool to China.

But either way NIL along with EUV has been one of the technologies considered for the manufacturing of next gen MRAM by Nankai:
​
"Obtained some representative work in key processes of micro-nano processing technology/ultra-precision manufacturing equipment and ultra-high density magnetic storage:

1) 7nm node extreme ultraviolet (EUV) lithography technology exposure agent research and development, 7nm Node/13nm period EUV interference lithography (IL) process, Si 3 N 4 mask manufacturing process for EUV/X-ray array technology;

2) Use EUVIL to prepare the smallest 20nm two-dimensional lattice that can be obtained by optical methods for the next generation of magnetic recording media;

3) 8/12-inch next-generation Sub-20nm spin transfer torque magnetic random access memory chip STT-MRAM process (comparable to the best Samsung process technology), 50nm resolution, 1:7.5, the world’s highest aspect ratio structure The 8/12 -inch nanoimprint equipment is used in the magnetic sensor array process;

4) Cooperate with GermanLitho/Tianren Micro-Nano Technology and Leuven Instrument industry-university-research institute to jointly develop special equipment focusing on magnetic sensor array/MRAM 2/4/6/8-inch nanoimprinting and 8/12-inch RIE/IBE dual engraving Etching technology exclusive etching equipment for magnetic materials."
Click to expand...
Hmm I was thinking in terms of how complex chips need more complex patterns which then need more multiples of pass throughs so if you’re dealing with deformities or alignment issues with either the wafer, stage, or press more complex chips are more prone to error stack. I guess it depends on how you break down your patterning steps though so maybe what I was thinking about is manageable. Also possible I guess that you don’t need to go full nanoprint for the whole workflow and just integrate that into steps that best fit the capabilities of the equipment.
 
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Changdian Technology (JCET) Subsidiary Increases Capital of 4.4 Billion Yuan to Take Second Phase Shares of Large Fund​


Recently, Changdian Technology announced that it will increase its investment in Changdian Technology Automotive Electronics (Shanghai) Co., Ltd. (hereinafter referred to as the "Target Company") by 4.4 billion yuan, of which the original shareholder Changdian Management will increase its capital by 2.326 billion yuan, and the original shareholder Xinxin Fund will give up Capital increase; new shareholders Big Fund II, State-owned Assets Management Company, Shanghai Fund II and Core Whale increased their capital to the target company by 864 million yuan, 700 million yuan, 270 million yuan and 240 million yuan respectively.

It is understood that Changdian Technology Automotive Electronics (Shanghai) Co., Ltd. was established in April 2023. The legal representative is Zheng Li and the registered capital is 400 million yuan. After this capital increase, its registered capital will increase to 4.8 billion yuan.
This capital increase is mainly to accelerate the construction of an advanced packaging base for large-scale professional production of automotive-grade chip products in Shanghai Lingang New Area, supporting domestic and foreign major customers and major industry partners, and oriented to the highly electrified and intelligent new energy vehicles. ization and comprehensively build a complete local supply chain of finished chip products.

Public information shows that Changdian Technology’s automotive chip finished product manufacturing, packaging and testing production base located in Lingang, Shanghai covers an area of more than 200 acres, with a factory area of approximately 200,000 square meters. The project started construction in August this year. It is expected that after the project is completed in early 2025, it will not only become the first intelligent "black light factory" production line built by Changdian Technology in China, but also become a benchmark factory for large-scale professional automotive electronic chip manufacturing in China, driving the entire industry chain to a higher level. performance, high reliability, and high automation.

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