Chinese semiconductor thread II
- Thread starter vincent
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Etching process prediction based on cascade recurrent neural network.
Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics
School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing, China
Department of Micro and Nano Electronics Engineering, Shanghai Jiao Tong University, Shanghai, China
Changxin Memory Technologies Inc., Hefei, Anhui, China
Abstract
Etching is one of the most critical processes in semiconductor manufacturing. Etch models have been developed to reveal the underlying etch mechanisms, which employs rigorous physical and chemical process simulation. Traditional simulation is very time consuming. The data-driven artificial intelligence model provides an alternative modeling approach. In this paper, a Cascade Recurrent Neural Networks (CRNN) is proposed to model and predict etching profiles. The etching profile is represented by polar coordinates and modeled by the recurrent neural networks, the corresponding etching parameters (e.g., pressure, power, temperature, and voltage) are integrated into the network through cascade combination layers. Experimental results on a dataset of 10,000 simulated etching profiles demonstrated the effectiveness of our method: compared with traditional etching simulation methods, CRNN can speedup 21,000× with an average error of less than 0.7 nm for 1 step prediction. Furthermore, compared to simple deep neural networks, the Mean Absolute Errors (MAE) could be reduced from 1.7329 nm to 1.3845 nm for 10 steps prediction. Finally, the effectiveness and accuracy of CRNN etching predictor is validated through fine-tuning on experimental data.
Software-defined process-near-memory architecture using 3D hybrid bonding integration
Abstract
With the unprecedented explosive growing amount of global data, the development of computing chips, which encounter bottlenecks such as power wall and memory wall, cannot satisfy the demanding requirement. This work proposes a software-defined process-near-memory (SDPNM) computing architecture implemented using 3D hybrid bonding integration. The software-defined chip architecture, featuring spatial computations and dynamic reconfiguration, innovates in a top-down manner to achieve high energy efficiency while maintaining flexibility after fabrication. The process-near-memory integration further advances the SDNPM chip in a bottom-up way to reduce the energy consumption of data movement while improving the bandwidth. Utilizing a relatively mature fabrication and bonding process can result in feasible solutions for both data-intensive and compute-intensive applications including digital signal processing and artificial intelligence. The logic die is fabricated in the SMIC 40 nm process and the DRAM die is fabricated in the PSMC 25 nm process. The hybrid bonding is implemented by XMC. The experimental results show that the energy efficiency of the proposed SDPNM chip is 33.1× better than the state-of-the-art FPGA ranging from 8.2× to 104.1×.
Yandong Micro plans to raise 4 billion yuan for a 12-inch integrated circuit production line project
According to the Semiconductor Industry Network, Yandong Microelectronics recently issued an announcement stating that the company plans to raise no more than 4.02 billion yuan from its controlling shareholder and actual controller Beijing Electric Control through a private placement. The net amount after deducting issuance expenses will be invested in Nortel Integrated's 12-inch integrated circuit production line project and to supplement working capital.
The announcement shows that the total investment of Nortel Integrated 12-inch integrated circuit production line project is 33 billion yuan. It plans to build a 12-inch integrated circuit chip production line. The products are mainly for display driver, digital-analog hybrid, embedded MCU and other fields, and build 28nm-55nmHV/MS/RF-CMOS and other special process platforms. The planned production capacity will reach 50,000 pieces/month after completion. The project focuses on mature processes of 28nm and above, focusing on core chip manufacturing in consumer electronics, industry, new energy, security, Internet of Things and other fields, improving chip production capacity, increasing the proportion of domestic chips, and further improving my country's integrated circuit industry ecology.
Yandong Micro said that the company was one of the first companies in China to build a 4-inch production line, and has since built a 6-inch production line, an 8-inch production line, and a 65nm 12-inch production line. The technical nodes of this project cover 28nm and above processes.
So first I am noticing she is using wafer area measurements. That is good.
Here's the wafer area measurement rankings.
It's hard to be tied for global #1 and keep growing so fast, according to her own metric.
let's not keep posting low quality sources.
If you need to see just how much capacity is added, you can take a look at what AMEC posted in its half year report.
China became world's large SME market in 2023 and it extended that lead in 2024. There is more capacity coming online in China than anywhere else.
If you need to see just how much capacity is added, you can take a look at what AMEC posted in its half year report.
China became world's large SME market in 2023 and it extended that lead in 2024. There is more capacity coming online in China than anywhere else.
FT's 2032 forecasts are likely based on publicly announced future planned capacity increases. I suspect many Chinese fabs have stopped publicly announcing all of their long term expansion plans so as to avoid giving out information that can be used by the US for sanction targeting and enforcement.
I just published 4 300mm fabs that are not SMIC or HH expanding capacity in the last few days alone.