petty..
people needs to know that CETC is the supplier for that 65nm dry DUV.
Chinese semiconductor thread II
- Thread starter vincent
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people needs to know that CETC is the supplier for that 65nm dry DUV.
Well is not known if the supplier is SMEE, CETC or both, the document doesn't specify the company. But yes CETC should be in the lithography list.
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Lianke Semiconductor's liquid phase silicon carbide crystal growth furnace was successfully accepted!
Lianke Semiconductor's liquid phase silicon carbide crystal growth furnace has made key progress. The liquid phase silicon carbide (induction) heating crystal growth furnace and the liquid phase silicon carbide resistance heating crystal growth furnace have been successfully accepted at the customer's site. The silicon carbide liquid phase crystal growth furnace equipment provided by Lianke Semiconductor is highly compatible with the customer's core process, which helps customers to grow low-cost and high-quality crystals in a visual way, and at the same time lays a solid foundation for Lianke Semiconductor in the field of silicon carbide liquid phase method.
First Experimental Demonstration of 3D-Stacked 2T0C DRAM Cells Based on Indium Tin Oxide Channel
School of Integrated Circuits and Beijing Advanced Innovation Center for Integrated Circuits, Peking University,
Wuhan National High Magnetic Field Center and the School of Integrated Circuits, Huazhong University of Science and Technology,.
In this letter, we provide the first experimental demonstration of 3D-stacked 2T0C DRAM cells based on indium tin oxide (ITO) FETs. The 3D sequential integration process steps cause negligible performance degradation to the bottom ITO FET including on-current, on/off ratio, subthreshold slope, and mobility, exhibiting excellent stability during the fabrication process of the top FET. Both layers of FETs show very small threshold voltage V th shift under positive bias stress measurement for 3,000 s, where the negative shift of V th is only about 0.045 V and 0.08 V for the 1 st and 2 nd layer FETs, respectively. The 3D-stacked 2T0C DRAM cell consisting of two ITO FETs shows excellent data retention time of 1,360 s and endurance over 10 11 , rivaling the counterparts based on planar structures. These results indicate the great potential of the 3D-stacked 2T0C DRAM cells for future 3D DRAM applications.
The absolutely full localization of mid-high end lithography machines optical components.
Sidetracking a bit here... One major reason is that RISC-V is not a very well-designed ISA. Some of the design choices are questionable at best. Qualcomm, Alibaba T-Head and even Huawei have their own modified versions of RISC-V. If you follow RISC-V news you can find that Qualcomm publicly proposed major fixes for RISC-V but got rejected.
RISC-V is good enough mostly for embedded cores but a somewhat flawed ISA for high-performance computing. Working with RISC-V for an extended period of time usually makes one appreciate how well-designed ARM AArch64 is. Unless either Qualcomm or Huawei is completely cut off from ARM so that they are forced to move on to an improved version of RISC-V, we will probably not see any serious efforts in RISC-V outside embedded markets.
Neither was ARM well designed back in the day until was taken seriously by Apple. Is like SMEE litho machines, will be not until companies decide to put then into heavy work that would improve.
Also I don't think so that Qualcomm, T-Head and Huawei have their own "modified versions" they may had added their own proprietary "extensions" to the base ISA, like GPU, NPU, SIMD extensions. Modifying the base ISA would made every software made until now incompatible by default and that I don't think is not goal.
The same was for ARM in the late 90s, people said "that will never defeat Intel" until Intel made it difficult to Apple to use their X86 ISA because Intel wanted to control the fabrication process, so Apple decided to go with ARM for the smartphone and other devices and Intel lost a huge opportunity that is paying till today. So looks like some company didn't learn their own history lesson. NEVER EVER PUT YOUR COSTUMERS INTO A CORNER.
The ISA is well designed for what it was intended to do. To be used by college hardware design classes on how to design modern CPUs. At UC Berkeley.
We joked about scaling all the way from embedded to server space when we originally delineated the ISA.
So you can go from RV32E all the way to RV128.
Little did we know how far the ISA would come. The biggest mistakes IMHO on the specification with regards to the server space are the lack of indexed memory addressing and performance with unaligned memory accesses. I did put those as desirable features on the initial specification, but the college students torpedoed that because it would have made their task of designing a CPU in a semester harder. So much for that.
I do think T-Head has some proprietary extensions which do add indexed memory addressing.
As for Qualcomm, much of what they have claimed RISC-V should add or remove, is bullshit and a bad idea. They are just being lazy and trying to turn RISC-V into ARM. For example the variable length instructions in RISC-V. They are actually a great idea to compress code size so you need less i-cache and have less faults. I usually joke that RISC-V is the most CISCy RISC processor.
And it is not like there is anything preventing you from supporting unaligned memory accesses in your own hardware implementation. It is just that it isn't mandatory as part of the spec.
As for the lack of flags you can blame me.
I demanded that to be part of the architecture to make it easier to make OoO superscalar processors.
Another thing it could use, I guess, is a proper multiple register save and restore instruction. While we did consider it, back then I didn't know about the ARM instructions, I had never coded in ARM assembler myself, and the x86 register save instructions are kind of useless anyway.
On hindsight I am not even sure if ARM had those instructions back when we came up with the initial draft RISC-V spec.
You can get RISC-V to work for high-performance computing even with the regular ISA. You will need a wider processor because you will have more ops because of the lack of indexed memory addressing and other things. But it is not like it is impossible to do one.
Good evidence for this is that people like Jim Keller have looked at the architecture and think there is nothing majorly wrong with it.
The ISA is also so extensible that if something does become a major issue it can be added later. The latest RVA23 spec is way more complete than the initial RV64GC.
RISC-V is probably the only current architecture designed from the outset to be able to support hypervisors in the future. And it also has more features that other architectures lack despite being that simple. It was designed to be extensible from the start. With the variable length instructions you get even more ISA space without bloating the code size.
A lot of people claim that the latest RISC-V profile with the builtin instruction compression always provides the smallest binaries of the major architectures. Even compared with CISC x86-64. So that is something. A lot of people overly focus on reducing the amount of instructions instead of code size. But they forget that while logic continues to shrink, memory (particularly SRAM) is shrinking way slower. It is important to keep the memory footprint down. If you keep going outside of the cache size and need to fetch memory from DRAM you will also slow everything down.
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I wonder if its mainly money related since a comprehensive license like an ISA license would need to be priced close to or above what the projected volume based license would generate from the licensee since the holder would be potentially giving up any upside revenue from increases in volume. I think the issue here is Qualcomm got their ISA license transferred from the Nuvia acquisition, who probably paid a lower price for the license from ARM since their projected sales would be different then say Qualcomm. From ARMs perspective Qualcomm is committing highway robbery on ARM by using someone else's ARM license to design out stuff they would normally buy from ARM.
I don't see this being an issue with Huawei because they probably paid handsomely for their ISA license, nobody would be stupid enough to sell a one time permanent license for something that could offset years of recurring licensing revenue without quoting it to at least match the projected recurring license fees. And if ARM were to try and do the same thing for Huawei, they might as well kiss their future in China goodbye which is at least 20% of revenue if not more so that's unlikely to happen unless it was forced.
