CoreShine Intelligent launches RISC-V architecture, domestically produced self-controllable AI SSD master chip XT6160, to safeguard the security of the supply chain and industrial chain under the new situation.
In order to create a SATA enterprise-level SSD master control chip that meets the needs of domestic independent control and has excellent performance, Xinsheng Intelligence and the packaging factory fully leverage their respective technical advantages. Through a series of chip circuit design and semiconductor manufacturing process collaborative optimization efforts, they reduce leakage current and operating power consumption, improve working environment temperature and engineering application reliability, achieve substantial benefits, and achieve design goals such as high performance, high reliability, high energy efficiency and high security for enterprise and data center applications .
The XT6160 main control chip is based on the mature 28nm HKC+ process technology , which achieves an excellent balance between performance and cost. All IPs of XT6160 are domestically produced and independently controllable. Among them, the core IPs such as SATA 3.2 Controller, 4KB LDPC , NAND Flash Controller (NFC), AXI Bus, ONFI 4.2 PHY, and commercial secret algorithms SM2/SM3/SM4 are independently developed by Xinsheng Intelligent, with a self-developed proportion of more than 60%. Other IPs are from domestic IP providers , thus realizing the full process of self-development and control from IP self-development, cooperation (cooperation with domestic IP providers) to chip design, manufacturing, packaging and testing.
RISC-V architecture, independent AI core
As an important member of the China Open Instruction Ecosystem (RISC-V) Alliance, CoreShine Intelligence has gathered the power of innovation for RISC-V. XT6160 is the first SATA III (6Gb/s) controller with an independent AI core launched by CoreShine Intelligence based on the RISC-V architecture in China. It is also another masterpiece after the launch of the world's first RISC-V architecture-based, 12nm process PCIe 4.0 controller in 2022.
The XT6160's AI core monitors the working status of NAND flash blocks, predicts the optimal read voltage and flash translation layer (FTL) parameters during the life cycle of the flash block based on ML/AI algorithms, and intelligently manages, calibrates, and optimizes related parameters, thereby effectively improving SSD read and write performance, lifespan, reliability, and energy efficiency.
T Superior performance, wide temperature design
XT6160 is based on an 8-channel 32 CE flash memory interface design, supports a channel interface rate of 800MT/s, is compatible with the latest 3D TLC/QLC particles from mainstream flash memory manufacturers, and supports a single-disk capacity of up to 16TB. It uses self-developed NFC Acc and Bufman hardware acceleration functions, with 128KB sequential read/write performance of up to 565/530 MB/s, and 4KB steady-state random read/write performance of up to 98K/60K IOPS , which is better than similar products in the industry. In addition, through QoS quality control technology, the consistency of read and write performance can be maintained at more than 95%, providing users with continuous and stable performance guarantees.
Taking into account the complex environment of different application scenarios, the operating temperature design target of XT6160 is set at -40℃ to 125℃. Through the coordinated optimization of chip design and production line process, research and application of process means including adaptive voltage regulation (AVS) technology, the chip power consumption is reduced and the product life and reliability are improved in ultra-high temperature environments of 85℃, 105℃, and even 125℃.
Green and energy-saving, one core for multiple uses
XT6160 adopts low-power designs such as clock gating and multiple voltage domains. The operating power consumption does not exceed 1.5W (DRAM cache mode) or 0.8W (no DRAM cache mode).
Data security protection throughout the entire life cycle
XT6160 is designed according to the National Cryptography Administration's security chip level 2 standard specification, with active logical and physical security protection measures, effectively resisting physical dissection, probes, reverse engineering and other cracking methods, protecting the physical security of the chip itself; during the startup and operation of the chip, it loads and runs legal and trusted firmware through signature verification to prevent illegal firmware tampering and ensure the safety of chip use. The chip integrates domestic commercial cryptographic algorithms SM2/SM3/SM4 and international cryptographic algorithm AES256 hardware acceleration engine, providing full life cycle encryption and decryption security protection for user data, and has almost no impact on the performance of the SSD, effectively ensuring the storage security of data and information.