Chinese semiconductor thread II

[tokenanalyst]

A medium-sized quartz sandstone deposit was discovered in Qingchuan County​

Recently, the geological results report of the Huangjiawan Quartzite Mine Exploration Project in Guifo Village, Qifo Township, Qingchuan County, submitted by the 10th Geological Brigade of Sichuan Province, successfully passed the review of the Sichuan Provincial Mineral Resources Reserve Review Center. On December 15, 2023, the project successfully passed the field acceptance organized by the Provincial Geological Bureau and was rated as excellent.

After review, the project discovered a medium-sized high-purity quartz sandstone deposit, which provided a new raw material base for Guangyuan City's silicon-based new materials and achieved good prospecting results. In recent years, Qingchuan County has accelerated the upgrading of the quartz sand industry, conducted detailed resource surveys, found out the county's quartz sandstone mineral resources, and vein quartz mineral resources, and conducted detailed surveys of the county's quartz sand mineral resources, with proven reserves exceeding 1 billion tons.

High-quality resources with a silicon content of more than 98% account for 65% of proven reserves; attract extension chains, transform the quartz sand resource enrichment advantages into industrial development advantages, and identify the quartz sand industry as the leading industry in Qingchuan Economic Development Zone; technological transformation and upgrading; formulating The quartz sand industry development plan encourages quartz sand processing enterprises to increase investment in technological innovation, forcing existing quartz sand rough processing enterprises to transform and upgrade to increase the added value of their products.​

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[tokenanalyst]

Large-Scale Vertically Interconnected Complementary Field-Effect Transistors Based on Thermal Evaporation​

State Key Laboratory for Mesoscopic Physics and Frontiers Science Center for Nano-optoelectronics, School of Physics, Peking University, Beijing, 100871 China​

Abstract​

With the rapid development of integrated circuits, there is an increasing need to boost transistor density. In addition to shrinking the device size to the atomic scale, vertically stacked interlayer interconnection technology is also an effective solution. However, realizing large-scale vertically interconnected complementary field-effect transistors (CFETs) has never been easy. Currently-used semiconductor channel synthesis and doping technologies often suffer from complex fabrication processes, poor vertical integration, low device yield, and inability to large-scale production. Here, a method to prepare large-scale vertically interconnected CFETs based on a thermal evaporation process is reported. Thermally-evaporated etching-free Te and Bi2S3 serve as p-type and n-type semiconductor channels and exhibit FET on-off ratios of 103 and 105, respectively. The vertically interconnected CFET inverter exhibits a clear switching behavior with a voltage gain of 17 at a 4 V supply voltage and a device yield of 100%. Based on the ability of thermal evaporation to prepare large-scale uniform semiconductor channels on arbitrary surfaces, repeated upward manufacturing can realize multi-level interlayer interconnection integrated circuits.

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[measuredingabens]

Large-Scale Vertically Interconnected Complementary Field-Effect Transistors Based on Thermal Evaporation​

State Key Laboratory for Mesoscopic Physics and Frontiers Science Center for Nano-optoelectronics, School of Physics, Peking University, Beijing, 100871 China​

Abstract​

With the rapid development of integrated circuits, there is an increasing need to boost transistor density. In addition to shrinking the device size to the atomic scale, vertically stacked interlayer interconnection technology is also an effective solution. However, realizing large-scale vertically interconnected complementary field-effect transistors (CFETs) has never been easy. Currently-used semiconductor channel synthesis and doping technologies often suffer from complex fabrication processes, poor vertical integration, low device yield, and inability to large-scale production. Here, a method to prepare large-scale vertically interconnected CFETs based on a thermal evaporation process is reported. Thermally-evaporated etching-free Te and Bi2S3 serve as p-type and n-type semiconductor channels and exhibit FET on-off ratios of 103 and 105, respectively. The vertically interconnected CFET inverter exhibits a clear switching behavior with a voltage gain of 17 at a 4 V supply voltage and a device yield of 100%. Based on the ability of thermal evaporation to prepare large-scale uniform semiconductor channels on arbitrary surfaces, repeated upward manufacturing can realize multi-level interlayer interconnection integrated circuits.

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Huh, it's nice to see progress on CFETs from Chinese labs. This being a simple preparation method to boot makes me wonder on the difficulty of bringing this to the fab.

 

[sunnymaxi]

Huh, it's nice to see progress on CFETs from Chinese labs. This being a simple preparation method to boot makes me wonder on the difficulty of bringing this to the fab.

Explain little bit more bro .. what is CFETs and where it is use..

 

[measuredingabens]

Explain little bit more bro .. what is CFETs and where it is use..

CFETs are vertically stacked transistors and the next step after GAAFETs. Instead of further horizontal scaling and trying to fit more transistors into a 2D area, the idea is to go 3D and start stacking transistors on top of each other for a doubling in transistor density.

 

[gelgoog]

The problem with stacking things on top of each other is chip cooling becomes much harder.

 

[tokenanalyst]

Domestic EUV

"The EUV lithography machine led by a certain domestic company is about 2-3 years slower than the immersion DUV lithography machine led by SMEE. The core component of the Nikon NSR lithography machine they bought uses a domestic Zeeman-birefringent dual-frequency laser for the laser interferometer. The interferometer was replaced. After the test, it was found that the measurement accuracy reached 6 nanometers, which greatly helped the calibration and further improved the accuracy of the machine. As for the finfet self-developed by a certain company, by expanding the gate area, the 7-nanometer finfet can match the overall performance of the 3-nanometer GAA, and it only requires DUV to do it, and the cost is lower. Therefore, a certain company has started production of equivalent 7nm-5nm chips this year."​

 

[Wahid145]

Domestic EUV

"The EUV lithography machine led by a certain domestic company is about 2-3 years slower than the immersion DUV lithography machine led by SMEE. The core component of the Nikon NSR lithography machine they bought uses a domestic Zeeman-birefringent dual-frequency laser for the laser interferometer. The interferometer was replaced. After the test, it was found that the measurement accuracy reached 6 nanometers, which greatly helped the calibration and further improved the accuracy of the machine. As for the finfet self-developed by a certain company, by expanding the gate area, the 7-nanometer finfet can match the overall performance of the 3-nanometer GAA, and it only requires DUV to do it, and the cost is lower. Therefore, a certain company has started production of equivalent 7nm-5nm chips this year."​

These are some important sentences. What are the sources for them?

 

[Blitzo]

Domestic EUV

"The EUV lithography machine led by a certain domestic company is about 2-3 years slower than the immersion DUV lithography machine led by SMEE. The core component of the Nikon NSR lithography machine they bought uses a domestic Zeeman-birefringent dual-frequency laser for the laser interferometer. The interferometer was replaced. After the test, it was found that the measurement accuracy reached 6 nanometers, which greatly helped the calibration and further improved the accuracy of the machine. As for the finfet self-developed by a certain company, by expanding the gate area, the 7-nanometer finfet can match the overall performance of the 3-nanometer GAA, and it only requires DUV to do it, and the cost is lower. Therefore, a certain company has started production of equivalent 7nm-5nm chips this year."​

I agree with Wahid, I think if possible, statements like this would benefit from indicating the source.

Also, what was the original formatting for the paragraph? It seems like only the first sentence is directly EUV related.

 

[tokenanalyst]

Xiamen University and Huawei cooperate to realize silicon/polycrystalline diamond bonding with ultra-low boundary thermal resistance​

In the modern electronics industry, thermal management is a key challenge. Semiconductor devices generate a large amount of waste heat, which must be effectively dissipated within a specified temperature range to maintain the device In the modern electronics industry, thermal management is a key challenge. Semiconductor devices generate large amounts of waste heat, which must be effectively dissipated within a specified temperature range to maintain device performance and reliability. This heat is transferred from device hot spots to heat exchangers for dissipation through layers and interfaces with significant thermal resistance. Recent research has focused on replacing ordinary substrates with highly thermally conductive materials to reduce overall thermal resistance. Diamond has the highest isotropy of any bulk material, making it an ideal heat-sink material for chip cooling. Simulations show that thin diamond can reduce thermal resistance by 20%. However, the progress of diamond coolers in practical applications is still limited. Achieving near-junction integration of diamond with low thermal boundary resistance (TBR) is a key challenge.

The successful integration of diamond on devices depends largely on the design of the diamond/semiconductor interface. Optimization of these interfaces is critical to minimize TBR while ensuring sufficient mechanical robustness to withstand long-term reliable operation. Additionally, high processing temperatures should be avoided as they are detrimental to implementation and semiconductor manufacturing processes. Additionally, the diamond/semiconductor connections need to exhibit sufficient thermal stability to withstand subsequent solder reflow (temperatures up to 300°C) during the chip packaging process.

Since diamond and semiconductors have extensive mismatches in terms of lattice constants, hardness, Debye temperature and coefficient of thermal expansion (CTE), solving these problems requires dedicated efforts. Over the past few decades, various attempts have been made, involving three main technical methods: epitaxial growth of semiconductors on diamond; direct growth of diamond by chemical vapor deposition (CVD) and the combination of diamond and semiconductors. However, these methods currently face challenges such as large TBR, high processing temperatures, low reliability, and limited efficiency.​

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