Of course, but the basic point still stands. Double patterning where you need it is incredibly costly to your unit economics, in general much more so than the other cost and workflow tradeoffs you’re making with EUV.
The supply chain costs are what they are, but the operational costs and, *especially*, production risks, are far bigger drivers of fabrication economics than the often fixed input costs of the equipment. EUV does involve some cost tradeoffs, but I think it’s pretty clear what the companies that run the fabs think of those tradeoffs given that they’re bringing EUV into their mature sub 10 nm lines, not simply using them for the nodes at the limits of the frontier.
Density *does* become less of a meaningful metric as you go smaller, but to be very clear that’s not the same thing as node shrinks becoming less meaningful. You don’t just do shrinks to pack more transistors in an area, but to make the transistors perform faster and more efficiently as well. As you go to sub 5nm nodes I think what we’ll see is less density scaling as transistors are spaced out more, but nonetheless performance gains from having faster more power efficient transistors.
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