Chinese semiconductor industry

BlackWindMnt said:

Does the p50 still use Sony I though that deal fell through at the last minute? That is why the p50 series no longer is using the well known RYYB sensor. Huawei had to postpone the launch of the p50 series.

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TSMC, in an effort to boost the consumer demand for its 3nm process, is planning to launch a Continuous Improvement Plan (CIP) for its EUV equipment, according to industry insiders. TSMC’s 3nm process is scheduled to enter mass production in the second half of 2022.

TSMC expects to raise its capital expenditure to US$100 billion for the coming three years, and 80% of which will be used on capacity expansion. However, concerns have been rising toward TSMC’s aggressive capital expenditure, fearing that it will hurt the foundry’s gross margins. Last month, reflecting exactly such a fear, Morgan Stanley downgraded TSMC’s stock rating to Neutral.

Zhan Jiahong, an analyst from Morgan Stanley, believes that TSMC’s extensive capital spending will drive its gross margins to below 50% in the long term. In the first quarter of this year, the margin stood at 52.4%. However, while TSMC’s revenues grew by 16.7% during the quarter, its product costs also grew by 15.2%.

As TSMC revealed, as of 2020, it already owned half of the world’s operating EUV lithography machines.

With EUV machines representing a large proportion of TSMC’s capital expenditure, their high costs will in turn be transferred to TSMC’s 3nm process. Fearing that the high price tag of its 3nm process would drive customers away and lead to lower gross margins, TSMC hopes that the EUV Continuous Improvement Plan will reduce the number of EUV machines it requires in the future by cutting down the EUV layers used in the 3nm process.

For N7+, TSMC has introduced EUV machines for the first time, using four EUV layers to reduce the application of multi-patterning techniques. For 6nm, five EUV layers are enquired, while 5nm reportedly use up to 14-15 layers. The 3nm process, in comparison, is expected to use up to 25 layers. With CIP, TSMC hopes to reduce the layers to 20.

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In R&D, vendors are working on an assortment of new

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technologies, such as scanners, resists, and masks. These will be necessary to reach future process nodes, but they are more complex and expensive than the current EUV products. For example, ASML is developing new EUV scanners, including a next-generation system with a staggering price tag of more than $300 million per unit. So far, it’s unclear if these systems will arrive on time.

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AndrewS said:

This is the most interesting part.

Japanese companies are ignoring US technology sanctions in order to supply Huawei?

If I were a Japanese executive, I'd be sweating and then working feverishly to bring down US technology content to 0% on all my products.



asia.nikkei.com/Spotlight/Huawei-crackdown/Chinese-components-double-to-60-in-new-Huawei-smartphone

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Using this new solution, Huawei can indeed make 14nm chips comparable to 7nm chips.​

tokenanalyst said:

Using this new solution, Huawei can indeed make 14nm chips comparable to 7nm chips.​

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jfcarli said:

DUV+ 3D stacking + Hisilicon's design expertise, with this expertise Huawei will circumvent EUV restrictions and show middle finger to under 5nm technologies.

I am a firm believer that DUV still has a huge, huge unexploited potential. AND IT IS CHEAPER.

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ZeEa5KPul said:

This doesn't mean that China's EUV efforts should be slowed down at all. China must explore all feasible avenues in future chipmaking.

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