Answering this question will require some more technical background information to be explained.
An Instruction Set Architecture (ISA) is (to simplify things) how the programmer communicates with the processor. An instruction is a command given to the processor to perform an action. An instruction set is the complete list of instructions for the processor.
ISAs can be broadly catergorized into two different architectural approaches:
(1) Complex Instruction Set Computer (CISC)
The goal of a CISC architecture is to complete a task in as few lines of assembly code as possible. The execution of a single instruction in a CISC architecture may take multiple clock cycles. The x86 architecture is considered a CISC architecture.
(2) Reduced Instruction Set Computer (RISC)
The goal of a RISC architecture is to keep the instructions simple. This means that all instructions in a RISC architecture should complete in one clock cycle. ARM, MIPS, RISC-V architectures are considered RISC architectures.
I will try to illustrate the difference between CISC and RISC using a multiplication example. The Arithmetic Logic Unit (ALU) performs operations on bits stored in the registers. Generally we move values from memory into the registers, perform the operation using the ALU and finally move the result from the register back into memory. (this is simplified a lot)
(i) Suppose we have a 8x8 memory array. E.g. 1:2 refers to the bits stored at row 1 column 2 of the memory array.
(ii) Suppose we have registers A, B, C, D, E, F.
(1) CISC multiplication.
We could have the following assembly code:
MULT 1:2, 2:2 -> Multiply the values stored at memory location 1:2 and 2:2. Store the result in memory location 1:2.
(2) RISC multiplication.
We could have the following assembly code:
LOAD A, 1:2 -> Load the value stored in memory location 1:2 into register A.
LOAD B, 2:2 -> Load the value stored in memory location 2:2 into register B.
PROD A, B -> Compute the product of the values in register A and B and put the result in register A.
STORE 1:2, A -> Store the value from register A into memory location 1:2.
MULT, LOAD, PROD and STORE are all instructions in the ISA that have to be implemented in hardware. The RISC approach does not implement a MULT instruction in hardware and results in more lines of assembly code due to having to explicitly state the load and store operations related to the register. The CISC approach also needs to do the load and store operations for the register, but the MULT instruction has all that implemented in the hardware.
At this point you might think isn't CISC just better because it has less assembly code? Introducing the performance equation:
time/program = (time/cycle) * (cycles/instruction) * (instructions/program)
Clock Time (time/cycle) can be reduced when transistor sizes decrease.
Clocks Per Instruction (cycles/instruction) is the average number of cycles to perform a single instruction. CISC architectures generally have more complex instructions that take more clock cycles to complete than RISC architectures.
Instruction Count (instructions/program) is the number of instructions in a program. In the previous example the CISC performed multiplication in a single MULT instruction, but the RISC architecture needed four instructions to complete a multiplication.
So to summarize CISC optimizes the instruction count at the cost of clocks per instruction, but RISC optimizes the clocks per instruction at the cost of instruction count.
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MIPS and RISC-V are both broadly classified as RISC type ISAs. RISC-V is an attempt to take lessons learned from previous RISC type ISAs (including MIPS) and create an improved and open-source RISC type ISA. From a technical context MIPS Technologies abandoning MIPS and moving to RISC-V can be viewed as moving forward with developing an improved RISC-ISA.
From a commercial context, MIPS Technologies is company that needs to make money. MIPS Technologies doesn't even design it's own hardware and only licences the MIPS architecture. The last Western commercial MIPS CPU was the 28nm Warrior series CPUs which very few people used. Only Loongson is still producing commercial MIPS compatible CPUs and there's a good chance Loongson don't even need to pay MIPS Technologies money for the license.
Loongson has spent a long time developing its own ISA and micro-architecture. For example, the 28nm Loongson 3A4000 commercial chip is compatible with the MIPS64 Release 5 ISA as well as its own self-developed LoongISA 2.0 ISA. All this is implemented in hardware with its GS464EV micro-architecture (micro-architecture is how the ISA is implemented in hardware, you can have different micro-architectures implement the same ISA).
