It says 38nm resolution and not node. Besides that there is also overlay which is different between the 2100i and the 1950i.
I dont think he meant that ASML refers to them as 7nm node machines, but that we (the forum users) call them that.
Chinese semiconductor industry
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That is the max resolution of CD achievable with the scanner, that for immersion lithography is around 35-45 nm depending on a lot of things, 7nm is the lithography process, in the case of immersion how accurate a scanner can "overlay" a previous layer with the new one using a complicated system of metrology, sensors, OPC corrections, map the wafer across the entire process ,mark finding and matching and so on, in the case of ASML they assure their clients that overlay metrology system can be use in a 7nm process node.
In the case of SMEE from sources that plan is to launch something similar to ASML NXT2000i, that is the reason why is taking so long, a huge jump considering that in 2017 that plan was to launch a immersion scanner that could be use in a 65nm process node, basically a single pattern scanner, then that was updated to a 28nm process, basically a double patterning scanner. And now because US escalation the plan, according to sources is to make an scanner similar to ASML 2000i.
You are clearly confused on many points.
1. 38nm is in reference to its minimum resolution.
2. NXT2050 was created targeting 5nm application in particular for secondary layers that complements the most critical EUV layers. It was not created specifically for China like this forum falsely identified it to be.
3. ASML would not identified their scanner and tied them to a specific node. What I’m trying to tell you is each model meets the minimum requirements needed to fulfill each specific node. E.g. the minimum configuration of 28nm is a NXT:1950, you can use anything more advanced. The minimum config for 10nm is NXT1980, etc.
NXT1950 is not capable to support the on product requirements of 20nm, so NXT1960 was created to add features and capabilities to serve 20nm node.
NXT1960 is not adequate for 16nm node (and D1x) requirements so NXT1970 with even more capabilities specifically to serve 16nm was created…etc, etc.
Every node has a specific in product performance requirement to match the feature size on the wafer. Let’s take overlay requirements, if you take the On Product Overlay requirements per node and match it to the minimum scanner model configuration, you’ll end up with what I shared. The issue here is most if not all of you have no idea what actual fabrication requirements per node are, so you are trying to make argument based on incorrect assumption that differentiation is between something simple as single and double patterning capability.
don’t worry about it…just ignore what I said as this sort of detail don’t really apply to what you need. Sorry I ever mention it.
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I googled "7nm rated scanner" and "28nm rated scanner"; nothing came up. You are the first person in human history to use these phrases in a public setting, so they are essentially your invention, presenting categories demarcated by unpublished criteria and thresholds set by you. As such only you have the power to determine whether SSA/800 fits in the "7nm rated scanner" category or not. So, unless you have indeed examined the detailed product specs and reached the determination in a well-informed way, saying it cannot do 7nm because it is not "7nm rated" seems circular logic to me.
Please read my other posts.
but let me ask you guys this, let’s just look at overlay requirement, do you know what the on product overlay spec is for the most critical layer is for 28nm/20nm/16nm/10nm/7nm/5nm/3nm? And what the minimum ASML/Nikon model required to meet requirement in each node? If you do, do the diligence to match up minimum scanner config with each node to verify if what I said is true or not.
If not, don’t argue. You can simply decide to dismiss what I said as incorrect or just believe me. Either way you won’t know for sure, it’s just a choice because you don’t even know why I’m correct or incorrect.
if you guys really want to engage in a meaningful debate, please first research the actual process requirements and scanner model capabilities and features. Don’t gang up on me without real data and try to convince me that I’m wrong. I’m more than happy to hear evidence that I’m sharing incorrect info.
by the way, you lost your argument at “I googled…”. Please don’t come at me that aggressively with something you don’t already know.
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I don't think you're understanding what we are saying. No one is saying your wrong. In fact I know what you're getting at is right.
I'm saying there's no way to know what a litho machine is "rated" at. So you can't just say it's 1:1 and the 2050i is rated at 7nm so it can make 7nm. Which is drastically different than EDA software which talks directly about the nodes they can go down to. With Chinese EDA saying they're at 14nm.
It's not that your wrong. Your comparison is bad is all I'm getting at.
No. You guys are not understanding what I’m saying. I’m telling you, those of us that know the process requirements and scanner performance do indeed match up the minimum scanner model configuration that way.
We have clear idea which model can or can not meet specific requirements. That’s our job. I don’t understand why you doubt we are capable to match up minimum scanner config on a per node basis. Heck, we do that on a per node, per layer basis.
Maybe I can turn this around and ask, if you know the requirement of the most critical layer of a given node, why won’t you be able to match it up to a minimum scanner configuration? If not, how do litho engineers decide which scanner model and what features to buy or not to buy? If it’s not possible to match minimum scanner config on a per node basis, are you assume we simply take a trial and error approach? Just curious why you think that way.
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The great thing about J6 is that it will remove dependence on Western chipmakers. It will end up removing Nvidia, QCOM, TI, Infineon and NXP from primary ADAS chip supply chain (the most expensive stuff in the car)
Here is an example in laid out from Freetech for Hongqi. You see Nvidia, TI & Infineon in there
This is an example of Leapmotor ADAS, you can see the heavy involvement of Nvidia, QCOM & NXP in there
With J6 covering everything, you don't need the Western stuff.
Just as importantly, Horizon now has shown the ability to develop high end SoC, so if it figures out pairing this up with 5G modem (maybe from Unisoc or something), then it can handle everything including the wireless communication
Here is an example in laid out from Freetech for Hongqi. You see Nvidia, TI & Infineon in there
This is an example of Leapmotor ADAS, you can see the heavy involvement of Nvidia, QCOM & NXP in there
With J6 covering everything, you don't need the Western stuff.
Just as importantly, Horizon now has shown the ability to develop high end SoC, so if it figures out pairing this up with 5G modem (maybe from Unisoc or something), then it can handle everything including the wireless communication
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