Or it’s just that SMIC doesn’t have much N+2 capacity.
Chinese semiconductor industry
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don't be too harsh ... just relax ..... I didn't know that Intel has successfully made 7nm ? when was it? and what product
well, it is just recently from this article .
And SMIC has made 7nm since last year (2022)
Just relax and civilised and don't need to "crucify" me
Was not trying to be harsh nor was that post a response towards you. The long post is just me trying to be thorough. So please don’t take offense to it.
Like most articles, this one is full of mistakes. The author is speaking from a general historical perspective without having good detailed knowledge on a process level.
Intel 10nm was in mass production back in 2018/2019 and had better capability than TSMC 7nm. Intel’s improvement over its 10nm was called 10nm enhanced but now called Intel 7 due to general population misunderstanding on where they are in the totem pole vs foundries. TSMC also had minor improved version to their 7nm called 7nm+. If we are to compare based on Apple-to-Apple method, it would look something like this:
SMIC N+1 < Samsung 7LPP < TSMC N7 < Intel 10nm < SMIC N+2 < Intel 7 < TSMC N7+
To truly appreciate the technological advancement between these nodes above, you’d have to understand the dimensional scaling used, the various DTCO techniques used that dictated the final transistor density number. They all used different combination of scaling and DTCO at a given node so unless you study these in detail, it’s hard to understand the advancement exhibited by each IDM and foundries. So, looking at the final cumulative metric, transistor density, would be the most general way to “rank” or compare on a process capability level.
and if we take it further, mixing in design differentiations, we compare actual chips on a “chip level”. Some designs are better than other or tailored to specific application, so even that is hard to make Apple-to-Apple conparison
and if we take it further, mixing in design differentiations, we compare actual chips on a “chip level”. Some designs are better than other or tailored to specific application, so even that is hard to make Apple-to-Apple conparison
beyond transistor density, the only real comparison of process capability with actual chip is when Snapdragon 8 was fabricated at Samsung and TSMC and could be used to compare process capability using chip of same design.
It’s just a misunderstanding…was not trying to target you in particular. Again, please don’t take my true intention the wrong way.
I forgot to mention Intel Fab D1 started fabricating Intel4 before their Irish Fab (Fab34). Fab34 is just starting to ramp. Most of the Intel4 capacity is coming out of Fab D1.
I have got a question. Since nowadays all these node process 28nm 14nm 7nm 5nm 3nm etc, are just trademark name，rather than actual physical dimension. How does it play into US export restriction rules？I mean，a fab can make chip with transistor density equivalent to TSMC 7nm, but call it 28nm, thus able to import required equipment？
The logic node naming were pretty consistent with the planar nodes (non-FinFET) with each node comparison with the size of litho cell (Contacted Poly Pitch and Minimum Metal Pitch shrinking at ~70% node to node. Basically the node naming convention, CPP and MPP all shrink by around 70% from node to node. Hence full nodes of 65nm, 45nm, 32nm, 20nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm….all shrink of 70% node to node).
he divergence of node naming didn’t start to happen until 16nm node. More specifically, it’s only Intel that insist on staying true to the old node naming convention. The node naming difference within the foundries are much smaller. The introduction of DTCO where different techniques to reduce cell height and cell width started at 16nm. Everyone started adopting different combination of DTCO resulting in it being more difficult to benchmark them with just the node naming convention. Most folks in the industry aren’t able to verbalize the difference between nodes of major fabs, even most of litho engineers in charge of production may not able to tell what their competition is doing. This is why there’s so much confusion and articles that can’t clearly articulate this clearly. Semiwiki has pretty good data on the actual feature dimension and DTCO technique used on a per fab basis; it’s not exact but pretty close. By the way, @tonyget, I see you are fairly active on semiwiki discussions.
With that said, the BIS export restriction last October was a bit vague but they addressed that with the updated restriction last month. The restriction is now refined to cover logic nodes that are non-planar, which covers all process nodes with finFET. But if somehow someone decide to game their rules more with planar node with transistor density close to a “traditional” 16nm, I’m sure BIS would
In DRAM, the naming divergence started around D2L (there’s two nodes in the 20ish nm node; D2L refer the lower of the two). For DRAM BIS this past month specified the 18nm cut-off is defined as what the “F” dimension of 6F^2 DRAM cell would be. Basically take the product of bitline pitch and wordline pitch to be cell area 6F^2; then it’s simple arithmetic to determine what “F” would be.
For 3D-NAND it’s fairly straight forward by simple count of the number of “wordline” layers (or level).
But if somehow someone decide to game their rules more with planar node with transistor density close to a “traditional” 16nm, I’m sure BIS would refine the definition to using a definition transistor density. And for DRAM, there’s already effort to adopt 3D-DRAM, capacitor less DRAM, or 4F2 DRAM; if and when that happen, a simple rule change to use bit density would come into play.
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One last point, the node naming may be more difficult to understand by laymen today so the media claims its mere marketing name. But that’s not entirely true.
Everyone uses a slightly different definition but in general the transistor density of any given fab/node do scale accordingly by a factor on a node to node basis. But since everyone produce different chip from different customer base, it’s not possible to use final transistor density of a final product from Fab A to compare to Fab B.
So, what you see as transistor density number used by credible technical analysis are theoretical transistor density numbers based on assumption of a chip with 60% NAND cells / 40% scanner flip flop (SFF) cells.
CPP, MMP, DTCO techniques are used to determine the cell height, and cell width of NAND and SFF cells to determine the theoretical transistor density. Basic info such as CPP, MMP, single or double diffusion barrier used, and number of metal tracks per cell; four piece of info would allow you to determine any fab /node combo’s theoretical transistor density.
The theoretical transistor density is then used to benchmark everyone’s process capability on an Apple-to-Apple comparison. So, the number used in a node naming convention is not mere marketing names, they do still mean something within any one fab. It’s just that there’s no longer one single shared definition used by all major fabs.
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If every fab's process is so different. Then how much work needs to be done，for chip designer to switch fabs for the same chip？For instance a chip was using TSMC 16nm，want to switch to SMIC 14nm？
Seems like since each fab have their own IP & EDA, it's not a straight forward process.
I would imagine you have to go through the entire taping out process, which from what I hear is long and expensive. for advanced nodes
Difference at 16nm family of nodes are small. But everyone adopted single diffusion barrier from double diffusion barrier at different point in time from 10nm to 7nm+. Number of tracks, CPP, MMP also varies.
for example, TSMC 7nm is with DDB, N+2 is with SDB. TSMC didn’t switch to SDB until 7nm+. SMIC N+2 also use larger CPP MMP than TSMC 7nm and 7nm+.
with everyone’s basic cell library being different (different CPP, MMP, cell architecture) it’s not trivial switching between fabs. Basically can’t simply transfer from one fab to another without additional work. New tape out would be required to tailor to each fab’s cell library.
This is also why you don’t see people swapping back and forth between fabs that frequently for advanced node for the same exact product.
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