These teardown shows that,even for WIFI chips,advanced node is important,28nm is not good enough,you need at least 14nm for advanced WIFI chips
2. Dehydration bake 150 °C for ten minutes
3. Vapor primer deposition of adhesion promoter HMDS
4. Spin coating the bottom antireflective coating (BARC)
5. Hot plate softbake to remove solvent
6. Spin coating the photoresist
7. Hot plate softbake to remove solvent
9. Hot plate post-exposure bake (PEB) for CA resists
10. Spray development with TMAH (Tetramethylammonium hydroxide) on spin equipment
11. Rinse with de-ionized water and dry with nitrogen flow
12. Hot plate + UV postbake to harden the resist image
13. Photoresist plasma descum to remove the residual photoresist
I think there is a big difference between FinFET and other process. If you watch their chip design, Hisilicon really utilizes SMIC 14nm for anything that doesn't have highest level of space/power constraintThese teardown shows that,even for WIFI chips,advanced node is important,28nm is not good enough,you need at least 14nm for advanced WIFI chips
HiSilicon Hi1105GFCV120 Wi-Fi 6/BT 5.2/SparkLink SoC Floorplan Analysis (IoTB)
This is a Basic Floorplan Analysis (BFR) of the HiSilicon Hi1105GFCV120_die found inside HiSilicon Hi1105GFCV120. The Hi1105GFCV120 was extracted from the Huawei Mate 60 Pro. The Hi1105GFCV120 die is fabricated using a two-layer passivation, ten layers of metal interconnect (one aluminum (Al) top metal layer and nine copper (Cu) layers), tungsten (W) contacts, shallow trench isolation (STI), a single polysilicon layer, and high-k metal gate (HKMG) finFET transistors. The observed minimum metal pitch contacted gate pitch and fin pitch are 68 nm, 96.0 nm and 48 nm, respectively. These critical dimensions, along with the observed features of the transistors, suggest that the Hi1105GFCV120 die was manufactured on 300 mm wafers using SMIC's 14 nm HKMG finFET process.
Broadcom BCM4398 Wi-Fi 7/BT 5.2 Combo SoC Floorplan Analysis (IoTB)
This report is a Basic Floorplan Analysis (BFR) of the Broadcom BCM4398 die found inside the Universal Scientific Industrial G5-602550 component. The BCM4398 die was manufactured on 300 mm wafers using TSMC's 7 nm HKMG finFET CMOS process. It features 17 metal interconnect layers (1 aluminum (Al) top layer, 16 copper (Cu) layers). The minimum observed metal, contacted gate, and fin pitches of 40 nm, 57 nm, and 30 nm, respectively.