Chinese semiconductor industry

I watched through that clip. Some of it seems nonsensical to me, but other stuffs made more sense

Like D0 = 0.3 -> 72% yield and start off at 0.6 - 50% yield. That seems plausible assumption on his part

earliest phones likely using earliest 9000S. I also subscribe to the theory that Mate 60 likely get the best made 9000S. Ones produced with more bad transistors are used for Nova 12 & MatePad Pro or something like that. I think semianalysis talked about binning, well I think there were some binning going on here, but the lower bin gets left over to lower end phones.

The breakdown in component area bw 9000 and 9000S is interesting

CPU took more space. Likely because you needed more space to get more transistors into those big cores where density is lower (HP density that he talked about). I wonder if this is something they can improve over time. @latenlazy I'm did it this way because they found it to achieve the highest performance to be a little less dense, but I wonder if the lower density hurts power consumption

GPU was a little smaller also using their own Maleeon design. He measured it to 1536 GFLOPS iirc (not sure how they got to that).
To put things in perspective, A17 does 2.15 TFLOPS. So A17's GPU is 40% more powerful
the structure is unique, different from Cuda, Mali, IMG & Andreno. Which is great, since in the event that those gets cut off, it's important Huawei can still produce this

ISP being 2x size makes sense, since the support for HDR Vivid. Very important for MatePad Pro

Modem also interesting since its area shrunk significantly with 4G/5G combined. Another support for Hisilicon's quality that they are able to improve performance by combining the two and shrinking real estate

The failure rate of those 7nm chips will likely go down as SMIC gains more experience making them.

Btw, I am not sure how accurate his density measurements are, but he is basically putting smic 7nm at close to 114 mmtr and around 11.4b transistors for the entire die.

A15 has 15b transistors
A16 has 16b transistors
A17 has 19b transistors
So it's not surprising that cpu and GPU performance on a17 is so much higher.

I would be interested in finding out how many transistors are actually usable out of that given what we know about dark silicon.

tphuang said:

Btw, I am not sure how accurate his density measurements are, but he is basically putting smic 7nm at close to 114 mmtr and around 11.4b transistors for the entire die.

A15 has 15b transistors
A16 has 16b transistors
A17 has 19b transistors
So it's not surprising that cpu and GPU performance on a17 is so much higher.

I would be interested in finding out how many transistors are actually usable out of that given what we know about dark silicon.

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1. 114M Tx/mm^2 is the theoretical transistor density something a kin to tsmc N7P (HD). Based on TechInsight breakdown, SMIC N+2 HD cell size would be about 5% larger.
2. 11.4B transistor on Kirin 9000S would be impossible based on what we know of the chip. You can't simply take the highest density number and multiply by the area of the SOC to determine the total number of transistors. Without studying in detail, I would put Kirin9000S total transistor count to mostly likley be somewhere between Apple A12 & A13. So we are looking at ~7.7B-ish transistors.

The above is simple assumption the relative size of HP vs HD on Kirin 9000S is similar to Apple Ax chips. It's widely believed Kirin9000S had larger higher performance core area (to compensate for the older process node and the larger cell size/lower transistor density that comes with it), this would ultimately take the actual transistor count even lower compared to the maximum HD use case theoretical number.


Here's some number off the top of my head as a reference for y'all:

Kirin 9000S has more die area at 107 mm2 than the A12 with 83 mm2.
So linearly interpolating between A12 and A13 to estimate transistor count makes little sense.

gelgoog said:

Kirin 9000S has more die area at 107 mm2 than the A12 with 83 mm2.
So linearly interpolating between A12 and A13 to estimate transistor count makes little sense.

Click to expand...

Good point, I forgot about that. Like I said, it was a quick and dirty estimate off my head.

I looked at the numbers again and normalized everything to the 107mm^2 Kirin9000S chip size. Assuming all else are the same (e.g. ratio of HD vs HP cells, etc.), then Kirin9000S could be between 8.8 to 9.6B transistors, so let's call it 9B transistors.

A sanity check with A17 makes sense. A17 is built on a process with more than twice the transistor density at slightly larger die area than Kirin9000S. A17 supposedly has 19B transistors....so, I think 9B transistor on Kirin9000S would be a good rough estimate.

hvpc said:

Good point. Like I said, it's an rough and dirty estimate and numbers off the top of my head. You can extrapolate what the transistor count would be on the larger chip. But the total transistor count would still be lower than 11B.

Click to expand...

IMO something around 9.5B is more likely.

SIOM is expanding its high end lithography R&D.

Involving many types of positions, the high-end equipment team of Shanghai Institute of Optics and Mechanics has issued a recruitment notice​

the website of Shanghai Institute of Optics and Mechanics - Shangguang Yingcai Network has recently released recruitment notices for high-end equipment teams, involving optical engineers, mechanical engineers, hardware circuit engineers, motion control engineers, software engineers, electrical engineers, embedded software and hardware engineers, Opto-mechanical structure engineers, laboratory construction and maintenance and other positions.
Among them, motion control engineers will participate in the selection, design, integration and optimization of software and hardware systems for multi-axis motion mechanisms, design control and compensation methods, and realize closed-loop control of precision motion mechanisms; embedded software and hardware engineers will be responsible for the operation of precision equipment. High-speed control, high-speed signal acquisition calculation and feedback design, FPGA software development, hardware debugging, etc. are required; laboratory construction and maintenance positions will assist in the construction of ultra-clean laboratories and be responsible for the daily operation, maintenance and management of laboratory water and gas lines.

tokenanalyst said:

SIOM is expanding its high end lithography R&D.

Involving many types of positions, the high-end equipment team of Shanghai Institute of Optics and Mechanics has issued a recruitment notice​

the website of Shanghai Institute of Optics and Mechanics - Shangguang Yingcai Network has recently released recruitment notices for high-end equipment teams, involving optical engineers, mechanical engineers, hardware circuit engineers, motion control engineers, software engineers, electrical engineers, embedded software and hardware engineers, Opto-mechanical structure engineers, laboratory construction and maintenance and other positions.
Among them, motion control engineers will participate in the selection, design, integration and optimization of software and hardware systems for multi-axis motion mechanisms, design control and compensation methods, and realize closed-loop control of precision motion mechanisms; embedded software and hardware engineers will be responsible for the operation of precision equipment. High-speed control, high-speed signal acquisition calculation and feedback design, FPGA software development, hardware debugging, etc. are required; laboratory construction and maintenance positions will assist in the construction of ultra-clean laboratories and be responsible for the daily operation, maintenance and management of laboratory water and gas lines.

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Click to expand...

I think this can be taken as fairly strong indication that SIOM is putting together an LPP prototype of its own alongside CIOMP.

hvpc said:

Good point, I forgot about that. Like I said, it was a quick and dirty estimate off my head.

I looked at the numbers again and normalized everything to the 107mm^2 Kirin9000S chip size. Assuming all else are the same (e.g. ratio of HD vs HP cells, etc.), then Kirin9000S could be between 8.8 to 9.6B transistors, so let's call it 9B transistors.

A sanity check with A17 makes sense. A17 is built on a process with more than twice the transistor density at slightly larger die area than Kirin9000S. A17 supposedly has 19B transistors....so, I think 9B transistor on Kirin9000S would be a good rough estimate.

Click to expand...

so if you look at his slides. he had High density areas at 115 MMTR and high performance (The big core of CPU) areas at 80 MMTR.

he ended up have N7P and SMIC 7nm at same density. He measured modem and medium cores all at HD density

Looks like he took a thorough look at K9000S. But without knowing how he measured density for different components, I would know idea of how legitimate his numbers are

Also, I don't understand this HP vs HD stuff? Is it common for a decently complex chip like in this case to have a "high performing" density and "high density" density?