Horizontally stacked nanosheets are emerging as an industry consensus for 5nm, according to IBM. These devices start with alternating layers of silicon and silicon germanium (SiGe), patterned into pillars.
Creating the initial Si/SiGe heterostructure is straightforward, and pillar patterning is similar to fin fabrication. The next several steps are unique to , though. An indentation in the SiGe layers makes room for an inner spacer between the source/drain, which will eventually be deposited next to the pillar and the space where the gate will be. This spacer defines the gate width. Then, once the inner spacers are in place, a channel release etch removes the SiGe. deposits the gate dielectric and metal into the spaces between the silicon nanosheets.
looks like SiGe is where industry is going with GAAFet.
TSMC uses Ge
Silicon has been the transistor channel material of choice throughout all CMOS technology generations up until our 7nm node. TSMC’s 5nm technology is the first advanced logic production technology featuring SiGe as the channel material for p-type FinFET.
TSMC is actively exploring alternative transistor channel materials as an additional degree of freedom in the design of high performance and low power devices. Silicon-germanium and germanium are examples of TSMC’s exploratory research work, which has been extensively published and in some cases recognized as highlights in international conferences.
We will see how this goes
If China is determined to shut this off, we will see if it is able to take advantage of having its own Ge resources