A quick question concerning the Huawei chips that are going to be presented soon this year (12/14 nm ones?) - is it yet known what parts of its development/manufacture/testing process have been done using Chinese assets and what parts done using external (imported) assets?
Chinese semiconductor industry
- Thread starter Hendrik_2000
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I think that’s probably intentional to make it harder to sanction.
PNCS SYSTEMS.
The company's cleaning equipment orders are at the level of 100 million yuan in 2018, 200 million yuan in 2019, more than 500 million yuan in 2020, 1.1 billion yuan in 2021, and 2 billion yuan in 2022. In terms of subdivided product structure, single-chip cleaning equipment is rapidly increasing in volume, and the value of new orders for single-chip cleaning equipment in 2021 will exceed 380 million yuan. The current planned products can be applied to advanced technology, mainly for storage (DRAM, 3D Flash), advanced logic products, and also cover some special processes, such as thin film technology, compound semiconductor, metal stripping process, etc.; at the same time, the company is continuing to invest resources in research and development of high Advanced process equipment (reaction chamber-18 chamber, supercritical cleaning, etc.).
The company's cleaning equipment orders are at the level of 100 million yuan in 2018, 200 million yuan in 2019, more than 500 million yuan in 2020, 1.1 billion yuan in 2021, and 2 billion yuan in 2022. In terms of subdivided product structure, single-chip cleaning equipment is rapidly increasing in volume, and the value of new orders for single-chip cleaning equipment in 2021 will exceed 380 million yuan. The current planned products can be applied to advanced technology, mainly for storage (DRAM, 3D Flash), advanced logic products, and also cover some special processes, such as thin film technology, compound semiconductor, metal stripping process, etc.; at the same time, the company is continuing to invest resources in research and development of high Advanced process equipment (reaction chamber-18 chamber, supercritical cleaning, etc.).
After TSMC its time for Samsung .. LOOL
Korean semiconductor industry on pace to record heavy Q1 operating losses
At least 2 trillion won for Samsung Electronics, potentially over 4 trillion won for Hynix.”
Operating losses for South Korea’s memory industry during the first quarter of this year may amount to trillions of won, analysts are predicting.
If Samsung Electronics records a quarterly deficit for its semiconductor sector, it will be the first in 14 years since the first quarter of 2009, shortly after the eruption of a global financial crisis.
Korean semiconductor industry on pace to record heavy Q1 operating losses
At least 2 trillion won for Samsung Electronics, potentially over 4 trillion won for Hynix.”
Operating losses for South Korea’s memory industry during the first quarter of this year may amount to trillions of won, analysts are predicting.
If Samsung Electronics records a quarterly deficit for its semiconductor sector, it will be the first in 14 years since the first quarter of 2009, shortly after the eruption of a global financial crisis.
Extending the Application of Capacitively Coupled Plasma Etching Tools to the Front-End-of-Line Fin-Cut Etching Process for FinFET Mass Production.
Semiconductor Manufacturing International CorporationAbstract
As FinFET scales down to advanced technology nodes, Self-aligned Quadruple Patterning (SaQP) scheme is widely deployed for Fin formation, where two mandrels (MD1 and MD2) and corresponding mandrel spacers (MD1SP and MD2SP) are patterned for accurate CD transferring. The Fin-cut etching process of the MD2SP Cutting is very critical for the patterning of the Standard Cell and the SRAM patterns. This work studies the application of the Front End of Line (FEoL) MD2SP Cutting process in both inductively coupled plasma (ICP) and capacitively coupled plasma (CCP) etchers. The mismatch between the two tools is observed and discussed in detail. For CCP tools, a degradation of line width roughness (LWR) and increase of critical dimension (CD) loading between dense and isolated patterns are observed. Compared with the ICP etchers, the CCP etchers have lower plasma dissociation and stronger physical bombardment of ions. Furthermore, it is harder to control the plasma density and directionality separately. To increase CCP tool applications in FEoL processes, we introduce a Silicon coating process to modify the photoresist (PR) during the CCP etching to harden the surface of the PR and enhance the LWR performance. Furthermore, the application of atomic layer etching (ALE) technology ensures the CD loading between the dense and isolated patterns. With the application of our study, we can broaden the application of CCP tools in FEoL for FinFET mass production.Looks like SMIC has manage to solved some issues on the etched resolution of patterns made with capacitive couple plasma etchers.
AMEC and Naura etchers?
What do you mean? What happened to tsmc? tsmc’s first two months’ revenue performance is better than last year’s.
A novel capacitively coupled plasma driven by hollow cathode radio-frequency discharges.
College of Science, Donghua University, Shanghai 201620, People's Republic of China
Member of Magnetic Confinement Fusion Research Centre, Ministry of Education of China, Shanghai 201620, People's Republic of China
Textiles Key Laboratory for Advanced Plasma Technology and Application, Shanghai 201620, People's Republic of China
New plasma sources with high density and low energy are required to process material surfaces in nanometers. In this study, an electrode integrated with a hollow cathode (HC) and capacitively coupled plasma (CCP) was developed. With the tool, a novel capacitively coupled plasma driven by the hollow cathode radio-frequency discharges (HC-CCP) was observed experimentally, and its properties in the center of the chamber were investigated by a Langmuir probe. The results demonstrated that the HC-CCP presents wide ranges of electron density (ne), between 109 and 1010 cm−3, and electron energy (Te), 3.5–6.7 eV. And their distributions can be controlled by the modulation of radio-frequency source power and frequency, work pressure, and bias voltage. Therefore, this plasma source can be applied to a new generation of material processing.
Tsinghua-German team published the raw data of the SSMB synchrotron experiment for and results were published as a in 2021. Researched started 5-6 years ago, and they only recently published the results. The Chinese Academy of Sciences (CAS) confirmed SSMB EUV as an industrial light source was adequate for industrialization and mass production lithography, there shouldn't be any concern about building a full-powered version.
This argument presents a limited and inaccurate view of the situation because it overlooks other possibilities that could explain why China has not built the SSMB yet, such as lack of resources, strategic priorities, or other technical challenges. The logical fallacy in this statement is a "False Dichotomy" or "False Dilemma" since it presents only two options, either SSMB is easy, and China would have built it, or SSMB is still in the R&D phase. In contrast, you see when an expert like @latenlazy opens his mouth, he doesn't speaks in absolute truth or black-white, but presents a balanced, professional, and nuanced language.
I doubt the first EUV prototype cost $150M, probably cost to $1 Billion given it's the first unit without benefit of economy of scale or mass-production benefits. So atleast compare apples-to-apples, not apples-to-orange costs.
I mean, they used an existing German synchrotron from 1990's and did slight modifications to produce SSMB EUV. An existing facility using 1990's tech! It means most of the components necessary already exist, it's just a matter of resources to build a fully powered dedicated synchrotron. Much easier than building an EUV LPP from scratch with less fail-points.
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