But this is for immersion lithography for leading edge nodes, it does not answer my question regarding dry lithography.
Chinese semiconductor industry
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KrF lithography at SMEE is currently only 110 nm capable but it is 90 nm capable from ASML.
ArF lithography is 57 nm capable on a single scan from ASML, and Intel used dry Nikon ArF tools for both their 65 nm and 45 nm processes (double patterning dry ArF for 45 nm). Yet SMEE only has it certified for 90 nm, only equal compared to ASML KrF tools.
What's holding SMEE back?
I believe that MIPS chips are (were?) popular in networking devices like those. LoongArch by most indications is still based on MIPS64
yes, but LoongArch has some additional instructions. They did a lot of work back in 2020/2021 to make it all their own. Since then, they've been fast tracking in pushing out new chips.
a little more on this. Looks like it was taped out and finished testing by December
Given how many E2000 CPUs have been put to use now, Loongson is catching up a little bit. But E2000 uses 14 nm process and 2K2000 uses 28 nm process. Given that China's 14nm capacity is limited, it would be good for 2K2000 getting more orders in the future so that some of that 12/14 nm process can be used to produce higher end CPUs.
Yes, I don't see the future for MIPS either
With that in mind, to clarify, I believe this batch of chips will be almost a drop in replacement for MIPS chips for current users.
Perhaps with an eye to sidestepping any possible sanctions like with ARM designed cores
There is at least 5 - 10 years before RISC-V can establish a mature ecosystem including developers.
With that in mind, to clarify, I believe this batch of chips will be almost a drop in replacement for MIPS chips for current users.
Perhaps with an eye to sidestepping any possible sanctions like with ARM designed cores
There is at least 5 - 10 years before RISC-V can establish a mature ecosystem including developers.
Ohh I think I misunderstood your question lol. You’re talking about going finer on resolution. I’d have to guess that limits to going finer involve a whole complex of factors including numerical aperture of the optics, stage precision (though maybe not as much since they need better precision for ArFi scanners), and the ecosystem of supporting products (as you mentioned earlier), but I think the basic logic comes back to business. You only have so much bandwidth and spending a substantial amount of that bandwidth refining lower resolution machines probably isn’t as urgent or as essential for business growth as trying to secure your capabilities on a much more advanced tech platform. Improving the capabilities of more mature platforms is often backfill work if your primary current business objective is about trying to push your frontier.
Quite often, while pushing those improved older light type nodes, you need to use double patterning. Since that cuts into the production of the system the machine is in they often compensate with increased speed of the machine. But to increase the speed to process a wafer, you need to boost the power of the light source, so you can do the same amount of exposure in less time. The finer processes might also require different optics.
Well, the resolution is determined k * wavelength/ Numerical Aperture.
The wavelength is determined by the source UV, DUV, EUV, XRay, electrons.
Numerical aperture is determined by the optics. Bigger mirrors in EUV that collect more light, lens-mirrors projection systems in immersion.
K is all the tricks that you put in the machine to help resolve resolution issues. Like computational lithography, special sensors and so on.
The throughput no only depends on the power of the source, but also on the photoresists, the speed and reliability of the wafer stage, even how fast can the wafers be measured and aligned.
having a powerful light source and slow wafer stage that takes a year to step and scan a wafer is not good. An underpower light source will be a bottleneck for a high speed wafer stage. A photoresists that takes a decade to be cured will be also a bottleneck for the entire process.
I guess for multiple patterning will depend on precision of the wafer stage, the alignment system, how well collimated the optics are to get rid of undesired effects and computational lithography.
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