Good article. Some technical details of Yangtze Memory X-Stacking
Chinese semiconductor industry
- Thread starter Hendrik_2000
- Start date
- Status
Without foreign companies, probably they have plenty of room, but in the future is possible that everything gets consolidated like in a big fish eat small fish scenario.
DRAM is by far more complex than 3D-NAND. The feature size, the error tolerances, and complexity are makes it more difficult to make leading edge DRAM chips.
The Big3 of memory fabs use fully depreciated old systems from obsolete DRAM nodes to build 3D-NAND chips. So, while YMTC uses new NXT1980 scanners, others use NXT1950, which are fully depreciated (and almost half the price when new). YMTC gets to use better tools than competition, but CXMT doesn’t have that luxury.
if you study how a DRAM chip is constructed vs. 3D-NAND, you’ll find DRAM chip architecture is much much more complex and difficult to build as compared to 3D-MAND.
it would be a mistake to misinterpret the situation as YMTC having better engineers than CXMT.
Nanda Optoelectronics: Wulanchabu nitrogen trifluoride project is advancing as planned
Jiweiwang news (article/Yang Yanrou) On December 30, Nanda Optoelectronics stated on the investor interaction platform that the nitrogen trifluoride project in Wulanchabu is advancing as planned.
In addition, Nanda Optoelectronics stated that a photoresist that has been verified by the company has been sold, and the amount of this photoresist is small, so sales are low. At present, the company has a number of ArF lithography products for testing in large domestic chip manufacturers. Customers are very cautious about the use of photoresist products, so the company actively communicates with customers in the process of photoresist development, and dispatches on-site engineers to cooperate with verification work to lay a solid foundation for mass sales.
Previously, in response to the impact of macroeconomic fluctuations on the company's performance, Nanda Optoelectronics stated that the company's mass-produced products include MO sources, semiconductor precursors, electronic special gases, photoresists and supporting materials, etc., which can be used in thin film deposition, photolithography, It is applied in multiple integrated circuit manufacturing processes such as etching, doping, and cleaning. In addition to being affected by the macro economy, the company's performance growth is more affected by electronic information technology and the integrated circuit industry, which is also an important reason why the company has achieved good growth in the face of economic slowdown in recent years.
Bosch fab is mostly power related chips, which require only iLine and KrF. The little 65nm capacity is for analog chips, for those ArF is indeed the most critical litho system needed. I don’t think they have many ArF scanners, this is why I assume very little capacity for 65nm.
SMIC and Huahong 45/40nm share same tool sets as 28nm, so the layerstack breakdown (ratio) between ArFi/ArF/KrF/iLine are mostly the same. Meaning, layers usually requiring only ArF on 45/40nm also uses ArFi. This is a “necessity” because SMIC/Huahong do not have dedicated fabs for each nodes, so they typically buy equipment for better nodes and find ways to use those tools for older nodes.
tsmc have multiple dedicated fabs for 45/40nm node. They use mostly ArF dry as the most critical litho tool. But there’s a few layers that uses ASML’s old ArFi scanners. They are by far more efficient with how they make their 45/40nm chips.
tsmc/UMC/GF have mostly been migrating their customers to move MCU from 45/40nm to 28/22nm.
Could you elaborate the technical detail? I couldn’t find it, perhaps something was lost in the translation.
Taking the three-dimensional hybrid bonding process as an example, it is to bond a logic wafer and a storage wafer face-to-face and then cut them apart, so that a chip obtained is formed by bonding two chips face-to-face. Realize the heterogeneous integration of memory chips and logic chips.
With the help of this heterogeneous integration technology, it has also successfully helped the breakthrough of domestic 3D NAND. For example, the long-standing X tacking technology in China is to independently process the peripheral circuits responsible for data I/O and memory unit operation on one wafer, while the memory unit is independently processed on another wafer. When the two wafers are completed, the X tacking technology only needs one processing step to bond the two through millions of metal VIAs (Vertical Interconnect Accesses, vertical interconnect channels).
**Hybrid bonding
In contrast, foreign competitors have been using the CNA architecture that places peripheral circuits next to the memory array on the same wafer. In the past two years, it has turned to the CUA architecture of making peripheral circuits first, and then growing a single wafer of storage arrays on it.
Professor Wei Shaojun said: "Although it seems that the long-lasting two-wafer bonded architecture seems to be more costly, and the CUA architecture seems to be lower in cost, but when the NAND stack reaches more than 300 layers, you will find that this The process of placing the peripheral circuits on the bottom and then growing them is more difficult as the number of stacked layers increases, and the yield rate is very low. In the end, it is still necessary to learn for a long time. A big factory like Samsung has also made it clear that it can achieve 1,000 layers with such a long-term solution. Why did the United States put the long term on the entity list this time, because he saw that Chinese manufacturers began to take the lead in technology. This shows that we are on the right track in technology. ”
With the help of this heterogeneous integration technology, it has also successfully helped the breakthrough of domestic 3D NAND. For example, the long-standing X tacking technology in China is to independently process the peripheral circuits responsible for data I/O and memory unit operation on one wafer, while the memory unit is independently processed on another wafer. When the two wafers are completed, the X tacking technology only needs one processing step to bond the two through millions of metal VIAs (Vertical Interconnect Accesses, vertical interconnect channels).
**Hybrid bonding
In contrast, foreign competitors have been using the CNA architecture that places peripheral circuits next to the memory array on the same wafer. In the past two years, it has turned to the CUA architecture of making peripheral circuits first, and then growing a single wafer of storage arrays on it.
Professor Wei Shaojun said: "Although it seems that the long-lasting two-wafer bonded architecture seems to be more costly, and the CUA architecture seems to be lower in cost, but when the NAND stack reaches more than 300 layers, you will find that this The process of placing the peripheral circuits on the bottom and then growing them is more difficult as the number of stacked layers increases, and the yield rate is very low. In the end, it is still necessary to learn for a long time. A big factory like Samsung has also made it clear that it can achieve 1,000 layers with such a long-term solution. Why did the United States put the long term on the entity list this time, because he saw that Chinese manufacturers began to take the lead in technology. This shows that we are on the right track in technology. ”
Attachments
-
1672410610810.png
Very interesting article. SCMP selectively quoted one tiny part and used it to misrepresent the theme of the entire speech! What he actually said is entirely the opposite of what SCMP says. Still, what can one expect of an organ that employs Minnie Chan?
I must state again that this is not a Huawei thread. You can post economic news or tech news about Huawei in the Science & tech thread or China economy thread. This is not it. This is a thread about semiconductor. I've frankly tolerated this for long enough. Any non-semiconductor related Huawei post will be deleted going forward.
And @seemlay10, we got our eyes on you. If you are sleepy, you will be banned very quickly.
And @seemlay10, we got our eyes on you. If you are sleepy, you will be banned very quickly.
Dongxin: 512M NOR Flash samples based on 48nm process will be available next year
Jiweiwang news (article/Yang Yanrou) Recently, Dongxin shares said in an institutional survey that the company currently has mass-produced 65nm process and 48nm process including 1.8V 64M-256M NOR Flash products, which can be used for the company's NOR Flash products next year. Customers provide 512M based on 48nm process and 1Gb samples by stacking. These medium and large-capacity products are mainly used in some industrial and high-reliability application scenarios. In addition, the company is also actively deploying 3.3V NOR products, enriching the product line so as to enter more terminal markets.
In terms of the SLC NAND competition pattern, Dongxin said that the current global SLC NAND production capacity is mainly in Samsung and Hynix in South Korea, Micron in the United States, Kaixia in Japan, and IDM companies such as Winbond and Macronix in Taiwan. At present, in terms of wafer foundry, we also hope to cooperate more actively with wafer factories, and get more production capacity support to lay the foundation for future market share. With the gradual withdrawal of foreign major manufacturers from this market, we believe that in SLC NAND There is still a lot of market space in this market.
- Status