antiterror13
Brigadier
wowwww impressive, I am not sure whether Samsung already have 232 layers
NAND doesn't require EUV so China isn't held back by sanctions in this area.wowwww impressive, I am not sure whether Samsung already have 232 layers
@dengyeye bro same with DRAM? CXMT seems silent at the moment.NAND doesn't require EUV so China isn't held back by sanctions in this area.
EUV is required for high-end DRAM so unfortunately CXMT will lag market leaders until China gets EUV. That's why they are silent relative to YMTC.@dengyeye bro same with DRAM? CXMT seems silent at the moment.
@dengyeye Thanks bro, so we can equates that packaging is more important than front end Litho?EUV is required for high-end DRAM so unfortunately CXMT will lag market leaders until China gets EUV. That's why they are silent relative to YMTC.
NAND doesn't require EUV because the key tech is high aspect ratio etching and tightly controlled deposition. it is very hard to double your memory density by halving critical dimensions in 1 axis, much less quadruple it by halving critical dimensions in the other axis. on the other hand it's very easy to add layers - up to a point. But at the point where adding layers is complicated it's EVEN HARDER to shrink critical dimensions.@dengyeye Thanks bro, so we can equates that packaging is more important than front end Litho?
NAND doesn't require EUV because the key tech is high aspect ratio etching and tightly controlled deposition. it is very hard to double your memory density by halving critical dimensions in 1 axis, much less quadruple it by halving critical dimensions in the other axis. on the other hand it's very easy to add layers - up to a point. But at the point where adding layers is complicated it's EVEN HARDER to shrink critical dimensions.
20nmso what lithography node that YMTC use?
probably the same as every other NAND producer: 30-50 nm, which requires immersion ArF. You can probably relax this to 65 nm and do dry ArF, which China already has. The state of the art is <20 nm, also immersion ArF. So it depends. Specifically to YMTC, they are 20 nm but I'll bet they have backup plans for the case that their immersion ArF gets cut.so what lithography node that YMTC use?
The company, which is currently using a 20nm process to make about 10,000 twelve-inch wafers per month with a 64-layer 3D NAND flash technology, expects to reach 200,000 wafers per month using either a 128-layer or 192-layer technology by 2022. Kau expects Samsung and SK Hynix will each probably have a monthly NAND flash capacity of about 300,000 twelve-inch wafers by 2022.
The gain from stacking 1 additional layer is doubling cell density so you can see why going 3D is far more economical than trying to shrink planar dimensions. State of the art right now is 128-196 layers.Unlike planar NAND, which reduced the cell size at each node, 3D NAND uses a more relaxed process, somewhere between 30nm to 50nm. “Scaling in 3D NAND memory capacity is achieved in a different way: by adding vertical layers,” said Nerissa Draeger, director of university engagements at . “In this memory structure, cell density increases directly with the number of layers in the stack.”