5 NM FIN SAQP PROCESS DEVELOPMENT AND KEY PROCESS
CHALLENGE DISCUSSION
Yushu Yang*, Bowen Wang1, Qiang Wu1, Yanli Li1, Yibo Wang2, Yuning Zhu2, Yongjian Luo2,
Weihao Lin1, Qingqing Wu1,Jianjun Zhu1, Shoumian Chen1, Ying Zhang2
1Shanghai IC R&D Center, Shanghai 201210, China
2Beijing NAURA Microelectronics Equipment Co., Ltd., Beijing 100176, C
When CMOS technologies entered nanometer scales, FinFET has become one of the most promising devices because of its superior electrical characteristics. The 5 nm FinFET logic process is the cutting-edge technology currently being developed by the world's leading foundries. With the shrinkage in size, the usage of various multiple patterning methods (e.g., Self-Aligned Double Patterning, SADP, or Self-Aligned Quadruple Patterning, SAQP, Litho-Etch-Litho-Etch, LELE, 2D cut) becomes more and more frequent. In this study, we will briefly introduce 5 nm logic key layer process approach with EUV photolithography technology and, as an example, present in detail the 5 nm Fin patterning process with a Fin pitch of 24 nm based on the SAQP patterning method. Key process challenges are also discussed such as Critical Dimension Uniformity (CDU) and pitch walking. Finally, we proposed the Module Technical Specification (MTS) of 5 nm Fin SAQP key process as a reference. Moreover, we co-work with NAURA to develop 5 nm Fin SAQP etch processes on domestic made etcher tool NAURA NMC612D with very good initial results.
