AMEC etchers have already been accepted for 5 nm process.
Finally people talk about etch and deposition lmao I was waiting for this.
The key challenge in etch is how to manage very aggressive chemistries such as fluorine and oxygen containing plasmas in a highly controlled way to achieve a huge variety of requirements (not all at once) including but not limited to:
1. Precision high aspect ratio etch for very deep, very narrow holes, for memory applications
2. High aspect ratio high speed etch for TSV, CMOS, packaging
3. Highly controlled large area etch for logic, perhaps even as precise as atomic layer etching
4.. Generally, high degrees of etch selectivity so only what you want to remove (oxides or nitride or resist) while avoiding what you don't want to remove (silicon or metal but also sometimes oxide/nitride)
5. Generally, etch uniformity across entire wafer or even multiple wafers which is a major challenge due to the relatively small dimensionality of plasma generators active region relative to the wafer size and high reactivity of the plasma.
6. Generally, extreme etch purity. Anything that reacts with wafer materials can also react with reactor chamber materials like aluminum and steel. These act as unintentional dopants if allowed to be exposed to the wafer. The exact coatings and materials used for the chambers to resist plasma and for plasma exposed components are highly advanced and much of the time, proprietary, in chemistry, fabrication and testing.
7. Inline process metrology for film thickness, wafer bow and plasma chemistry to adjust the reaction parameters (wafer chuck temperature and heating rate, plasma generation and chemical feed)
I can get into deposition but that's going to be some huge wall of text too.
