Chinese semiconductor industry

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Hyper

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The Institute of Microelectronics of the Chinese Academy of Sciences has made important progress in the research of multi-modal ferroelectric storage and computing integrated FinFET devices and unit circuits.​

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The School of Integrated Circuits of Tsinghua University made a new breakthrough and realized the first sub-1 nanometer gate length transistor​


Recently, the team of Professor Ren Tianling from the School of Integrated Circuits of Tsinghua University has made a major breakthrough in the research of small-scale transistors. For the first time, a transistor with a gate length of sub-1 nanometer and good electrical performance has been realized.

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This is probably the smallest we can ever go . This will probably be the final record. We won't go much smaller.
 

AndrewS

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@tokenanalyst Wow!!! with Chinese new year break factor in (10 days), that is really impressive. We may be looking at net profit over $2 billion. :D

I suspect the fabs were still running at full capacity over Chinese New Year.

Remember the cycle time is 3+ months for a chip and labour costs are minimal compared to the cost of the equipment and facilities.
 

tokenanalyst

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Changdian Technology (JCET): The company's full range of XDFOI solutions will enter production in the second half of the year​


Changdian Technology stated on the investor interaction platform that the full range of XDFOI solutions will expand more possibilities for heterogeneous integration with unique technical advantages. The program will enter production in the second half of the year.

It is reported that last year, Changdian Technology announced the official launch of the XDFOI full series of extremely high-density fan-out packaging solutions. The heterogeneous integration that can effectively improve the IO density and computing power density in the chip is regarded as a new opportunity for the development of advanced packaging and testing technology. The packaging solution is a new type of TSV-free wafer-level ultra-high-density packaging technology. Compared with 2.5D through-silicon via (TSV) packaging technology, it has the characteristics of higher performance, higher reliability and lower cost. The solution can realize multi-layer wiring layers while the line width or line spacing can reach 2um. In addition, it adopts the extremely narrow pitch bump interconnect technology, the package size is large, and it can integrate multiple chips, high-bandwidth memory and passive device.

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tokenanalyst

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JCET Group Releases XDFOI Solutions Enabling Flexible Heterogeneous Integration​

Key Highlights
l XDFOI™, a family of high-density fan-out packaging solutions, is an innovative wafer-level packaging technology designed to provide cost-effective solutions with high integration, high-density interconnection and high-reliability for the heterogeneous integration of chipsets, that are in high demand
l Application scenarios includes FPGAs, CPUs, GPUs, AI and 5G, all of which require high integration and computing performance
l Product validation and mass production are expected to be completed in 2H 2022

Shanghai, China, July 6, 2021 – JCET Group, a global leading provider of integrated circuit (IC) manufacturing and technology services, today announces the official launch of XDFOI™, an innovative solution for ultra-high-density fan-out packaging. This revolutionary technology will provide cost-effective solutions with high integration, high-density interconnection and high-reliability for the heterogeneous integration of chipsets, which are in high demand . This innovation from JCET Group will take its advanced chipset backend manufacturing to new heights.
The XDFOI™ high-density fan-out package solution is a new silicon based, TSV-free, ultra-high-density wafer-level packaging technology with higher performance, higher reliability and lower cost compared to 2.5D TSV-based packaging technologies. XDFOI™ enables multiple redistribution layers (RDL) with line width and line spacing down to 2 micrometer. In addition, the extremely narrow bump pitch interconnect technology and large package size allow for the integration of multiple chips or chiplets, high bandwidth memories, and passive components.
The XDFOI™ solution portfolio greatly reduces system cost and package size by integrating different functional devices in a system package with a wide range of applications. XDFOI™ primarily targets FPGA, CPU, GPU, AI and 5G applications, with demanding requirements for integration and computing performance to provide several functional chips (Chiplets) with Heterogeneous integration Package (HiP) solutions.
Dr. Choon Heung Lee, CTO of JCET Group, said, "Moore's Law is slowing down, while the rapid development of information technology and the accelerated spread of digital transformation have stimulated a large number of diversified computing power needs. This market demand makes heterogeneous integration a new opportunity for advanced packaging technology, as it can effectively increase the IO density and computing performance within the chipset. JCET’s XDFOI™ solution will offer diverse options of heterogeneous integration for the customers’SoC as well as chiplets with unique technical advantages. Customer trials of the JCET XDFOI™ solution portfolio will begin soon and mass production is expected to begin in the 2nd half of 2022."
Mr. Li Zheng, CEO of JCET Group, said, "JCET has been developing cutting edge technologies based on our rich technology accumulation and industry-leading R&D capability in both packaging and test. The launch of the XDFOI™ solution portfolio not only demonstrates our strong technology innovation capabilities, but also represents a crucial step towards our goal of enabling disruptive breakthroughs in advanced packaging technologies. JCET will continue its relentless pursuit of technology leadership and deepen its close synergy with the industry ecosystem to jointly contribute to the sustainable development of the IC industry."

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tokenanalyst

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This is probably the smallest we can ever go . This will probably be the final record. We won't go much smaller.
I think we are approaching the economic limits of smaller transistors, even with EUV which is increasing the cost of semiconductors fabs by a lot, the cost of even designing the chips are in newer nodes is increasing exponentially.

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I think that advanced packaging (geometrical scaling) could potentially become the cost effective alternative to get more computational power while keeping the cost down and that could be one of the three potential future problems for ASML who has made a lot of investment in EUV taking in consideration that will be widely adopted.

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Han Patriot

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Yes i think CETC will eventually supply ICs to Russia. CETC has its own FABS as well which produces Chips for the Military and Space Programs.
CETC is also working on its own 28nm DUVL which will be available soon.

China has already developed localised Semiconductor manufacturing equipment for 45nm, 65nm and 90nm IC production.
This means certain Chinese FABs which use this locally made equipment can supply Russia.
This equipment can also be supplied to Russian FABs to replace their Western Equipment.
Also there is a huge market in China for second hand Semiconductor equipment and parts.
Russian FABS can buy these parts and other consumables like photoresists and gases and operate their current FABS for a long long time.

Western attempts to shut down the Russian Semiconductor Industry will basically just fail.
There is always a way and the Russians and Chinese are survivors. We will always find a way to circumvent this. Thats the difference between vassal states and peer states, sovereignty is above all. No McD or Nestle, create your own brands and let them grow, then export the brand to developing countries. The battle is in Africa, Asia and South America. Europe and N.A are already a matured market with alot of old oligarchies. Now I understood why Xi wanted to create BRI, it's essentially a new trade system with RMB at its core.
 
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