Chinese semiconductor thread II

[tokenanalyst]

Qier Electromechanical temperature control for a 14nm lithography process.

 

[latenlazy]

Defects can be reduced by better metrology and process optimizations. The industry did that for the 7nm and 14nm nodes with multiple patterning with immersion. My guess is, what cannot be overcomed by the fab is the low throughput of a tool, is it to manufacturer to optimize the tools the meet the fab requirements.

Yes but adding 2-4x more steps and being forced to repair/throw out more wafers from tolerance stacking errors also affects throughput. It’s not a clean win.

 

[tokenanalyst]

Yes but adding 2-4x more steps and being forced to repair/throw out more wafers from tolerance stacking errors also affects throughput. It’s not a clean win.

So you are confident that if Huawei-SMIC has access to the NXT:2150i or a domestic equivalent one they wouldn't be able to make 5nm to 3nm equivalent nodes with decent yields?

Just a reminder that they are doing 7nm and close to 5nm with possible the NXT:1980i and the NXT:2000i

 

[jx191]

you are making a lot of assumptions here without anything to back them up.

All I'm concerned about is the bottleneck for HBM3 now that news has come out about CXMT delaying their rollout despite all the good news about the financial side of things.

Specifically whether or not Huawei can produce enough 950DTs for the supernodes this year because they will need lots of HBM capacity. I'm just assuming that if CXMT cannot produce HBM3 at scale, Huawei will struggle to make their supernodes in reasonable numbers which wouldn't be great.

 

[latenlazy]

So you are confident that if Huawei-SMIC has access to the NXT:2150i or a domestic equivalent one they wouldn't be able to make 5nm to 3nm equivalent nodes with decent yields?

Just a reminder that they are doing 7nm and close to 5nm with possible the NXT:1980i and the NXT:2000i

N+3 isn’t a “proper” 5 nm. Huawei and SMIC clearly had to relax density requirements and still had yield problems despite that design concession, so yeah, I would not bet on the idea that having a better DUVi resolves these issues. Let’s be realistic here.

 

[tokenanalyst]

N+3 isn’t a “proper” 5 nm. Huawei and SMIC clearly had to relax density requirements and still had yield problems despite that design concession, so yeah, I would not bet on the idea that having a better DUVi resolves these issues. Let’s be realistic here.

With NXT:1980i maybe not but with the 2150I I would.

 

[tokenanalyst]

Huawei and SMIC are betting on strict process control and metrology, so is TSMC with Low NA instead of High NA.

 

[latenlazy]

With NXT:1980i maybe not but with the 2150I I would.

That’s a blind bet imo, but I don’t think we’ll ever see that proposition tested.

 

[tokenanalyst]

That’s a blind bet imo,

So you think stooges are wasting their time banning immersion? What is the obsession of industry stooges to ban scanners above the 1980i?

but I don’t think we’ll ever see that proposition tested.

That will require access to 2150i.

But you maybe right one thing, I think the immersion scanner will not be develop to go beyond the 1980i or the 2000i, looks like they going all the way to High NA EUV in one single jump.

 

[tphuang]

All I'm concerned about is the bottleneck for HBM3 now that news has come out about CXMT delaying their rollout despite all the good news about the financial side of things.

Specifically whether or not Huawei can produce enough 950DTs for the supernodes this year because they will need lots of HBM capacity. I'm just assuming that if CXMT cannot produce HBM3 at scale, Huawei will struggle to make their supernodes in reasonable numbers which wouldn't be great.

HW according to its own presentations makes its own HBM standard which I assume it does its own advanced packaging (since it has the patent for that). You are basing projection of their 950DT production on some Korean Media article about CXMT HBM3. How exactly are these things related?