The biggest problem for ASML is that they have the production of some critical components in the US. Like some wafer stage technology and alignment sensors in ASML Wilton in Connecticut and Light sources in ASML CYMER in San Diego, stooges can just block those exports and given the stupidity of the current Japanese government is likely that they could manage to get Gigaphoton too.
Chinese semiconductor thread II
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Shenzhen Pinghu Laboratory: Research on 8-inch 200 μm 4H-SiC Thick Film Homoepitaxial Growth for Ultra-High Voltage High-Current Power Devices
A team led by Professor Wan Yuxi at Shenzhen Pinghu Laboratory has successfully achieved high-quality growth of 8-inch, 200 μm thick 4H-SiC homoepitaxial films. This advancement is critical for developing ultra-high voltage (10 kV–20 kV) and high-current power devices used in new energy vehicles, AI data centers, and industrial applications. The team achieved:
- Precision Control:Using a vertically inlet hot-wall CVD system, the team optimized gas distribution and substrate heating (1600°C). This resulted in:
- Thickness Uniformity: As low as 0.74%–0.95% across the wafer.
- Target Accuracy: Final thickness measurements deviated by only ~1% from the goal of 200 μm.
- Doping Consistency: Achieved uniform n-type doping concentrations (~3.92% non-uniformity) and precise p-type doping (>99.9% purity relative to substrate detection limits), essential for IGBT structures.
- Defect Suppression: By optimizing the growth rate (25 μm/h) and TMAl flow, they reduced triangular defects from 2.23 cm⁻² to just 0.5 cm⁻². This significantly increased usable wafer area:
- IGBT structures: Usable area improved to 46.5%.
- Diode/MOSFET structures: Usable area reached an impressive 96.9%.
- Material Quality:The films exhibited excellent electrical and physical properties, including:
- Minority carrier lifetime of >5 μs (meets requirements for bipolar devices).
- Extremely smooth surfaces with RMS roughness under 0.3 nm and no macro-steps or step bunching.
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Achieving picometer-level wavefront repeatability with an enhanced environmentally robust point diffraction interferometer
Abstract
Although dual-fiber point diffraction interferometers offer sub-nanometer accuracy in wavefront aberration metrology for lithographic projection objectives, their widespread adoption is constrained by stringent environmental requirements, resulting in high costs and extended development cycles. These limitations originate from the inherent mechanical phase-shifting mechanism and high sensitivity to environmental disturbances, which collectively degrade measurement repeatability under conventional laboratory conditions. Since repeatability dictates the practical accuracy after system error calibration, suppressing random errors and enhancing the environmental robustness of ultra-precision interferometers in a non-ideal environment have become critical challenges.This study presents a novel point diffraction interferometer with enhanced environmental robustness for picometer-level wavefront repeatability. The system incorporates a custom-developed acousto-optic modulator driver that achieves sub-millihertz frequency stability even under low-frequency-difference conditions, substantially reducing random errors. By utilizing high-frequency heterodyne signals, which are inherently resistant to environmental noise, and combining them with a downsampling technique, the conflict between high-frequency modulation and limited camera frame rates is resolved, thereby mitigating environmental impacts on phase shifting.
Additionally, a Hybrid HEFS-Fourier Algorithm is introduced to match the high-speed sampling capabilities of the proposed system. An experimental setup is implemented on a platform without air-flotation vibration isolation to measure the wavefront aberration of the test objective and evaluate the wavefront repeatability under two measurement modes. Results from 32 consecutive measurements within 5 minutes under non-ideal conditions verify the system’s capability for ultra-high, picometer-level repeatability, with values of 18.11 pm RMS for the point diffraction measurement mode and 1 pm RMS for the system errors measurement mode.
Research on Multi-Dimensional Grating Interferometry Models and Dynamic Error Compensation Mechanisms for 14 nm Lithography Machines, funded by the Guangdong Basic and Applied Basic Research Foundation Project, duration: 2021.10 – 2024.09, Principal Investigator.
Huahong's net profit increased more than fivefold in the first quarter, with its "memory" business likely being the biggest contributor.
On May 14, 2026, Huahong Semiconductor released its first quarter financial report, revealing a dramatic turnaround driven by strategic efficiency gains and robust demand for specialty memory. While the company reported an operating revenue of RMB 4.625 billion (a year-on-year increase of 18.22%), its profitability metrics were exceptionally strong: net profit jumped by 513.10% to reach RMB 139 million, representing more than a fivefold increase from the previous period. This divergence between steady revenue growth and explosive profit expansion highlights the effectiveness of management's focus on cost reduction and process optimization during a complex global supply chain environment.
The primary engine behind Huahong's financial success was its embedded non-volatile memory business, which accounted for over 40% of total revenue in Q1. This segment saw a staggering 41.7% year-on-year growth, bolstered by increasing adoption across industries requiring long-term data storage within system-on-chip architectures. Stand-alone non-volatile memory also contributed significantly to the top line, growing by over 33%. In contrast to the massive scale of mainstream memory giants, Huahong's success in these smaller market segments demonstrates its ability to capture value from high-growth verticals like automotive electronics and IoT devices, where integrated storage is becoming a standard requirement for next-generation computing hardware.
Looking ahead to Q2 2026, Huahong Semiconductor remains optimistic about stabilizing its operational metrics. Company management expects both sales revenue and gross profit margins to improve, with projections for a gross margin range of 14% to 16%. Chairman Bai Peng attributes this potential improvement to continued cost efficiencies and the strengthening positive demand signals observed throughout the quarter. While Huahong acknowledges that its financials will remain structurally below those of leading memory chip manufacturers due to the nature of its product portfolio, it maintains its strategic commitment to becoming a global leader in specialty process foundry services, firmly planted in the emerging markets of power devices, analog chips, and advanced logic for the connected future.
The primary engine behind Huahong's financial success was its embedded non-volatile memory business, which accounted for over 40% of total revenue in Q1. This segment saw a staggering 41.7% year-on-year growth, bolstered by increasing adoption across industries requiring long-term data storage within system-on-chip architectures. Stand-alone non-volatile memory also contributed significantly to the top line, growing by over 33%. In contrast to the massive scale of mainstream memory giants, Huahong's success in these smaller market segments demonstrates its ability to capture value from high-growth verticals like automotive electronics and IoT devices, where integrated storage is becoming a standard requirement for next-generation computing hardware.
Looking ahead to Q2 2026, Huahong Semiconductor remains optimistic about stabilizing its operational metrics. Company management expects both sales revenue and gross profit margins to improve, with projections for a gross margin range of 14% to 16%. Chairman Bai Peng attributes this potential improvement to continued cost efficiencies and the strengthening positive demand signals observed throughout the quarter. While Huahong acknowledges that its financials will remain structurally below those of leading memory chip manufacturers due to the nature of its product portfolio, it maintains its strategic commitment to becoming a global leader in specialty process foundry services, firmly planted in the emerging markets of power devices, analog chips, and advanced logic for the connected future.
AMEC Cryogenic etching competing tool against LAM Cryogenic tools, well, not really competing because LAM is banned from selling theirs in China
AMEC Cryogenic Etching Tools Has Been Deliver For Verification
As the company's cornerstone business, etching equipment became the core driver of first-quarter revenue growth. Yin Zhiyao explained that the company's shipments of high-end etching products for advanced logic and advanced memory devices have increased significantly, and several key etching processes adapted to advanced logic mid-sections and ultra-high aspect ratio memory scenarios have achieved large-scale mass production.
Yin Zhiyao further stated that the company's dielectric etching products continue to maintain rapid growth, and the next-generation 90:1 ultra-high aspect ratio low-temperature etching equipment has been delivered to clients for verification. Currently, the company has fully covered various ultra-high aspect ratio process requirements for memory etching, and its technical strength continues to benchmark against international leading levels.
While consolidating its leading position in the etching business, AMEC continues to improve its product portfolio. In terms of thin film equipment , it has successfully developed tungsten series thin film deposition equipment, ALD titanium nitride, ALD titanium aluminum, ALD tantalum nitride and other products, as well as molybdenum metal deposition equipment.
Yin Zhiyao revealed that the company's PECVD equipment, which uses a very high frequency decoupled reactive ion plasma source and is equipped with 16 reaction stages, is progressing smoothly with various verification efforts from customers. The newly developed CuBS PVD multi-reaction-cavity integrated equipment significantly reduces the resistivity of BS compared to standard equipment at home and abroad, and increases the output rate by 50% to 100%. It has been recognized by several leading customers and has been delivered to advanced logic device R&D lines in China for verification.
The company is currently simultaneously advancing the development of more than 20 new equipment in six major categories. At present, it has launched a full range of thin film equipment products, including LPCVD, ALD, EPI, PVD CuBS, and PECVD. Many LPCVD and ALD equipment adapted to advanced logic and advanced memory processes have been commercialized and delivered; the etching equipment has achieved full coverage of process nodes from 65 nm to 3 nm and more.
When discussing the accelerated development of new products, Yin Zhiyao told the reporter from Science and Technology Innovation Board Daily that the company has achieved modularization and maturation of core technologies. New product development only requires the targeted development of 30%-40% of customized modules, while the remaining 60%-70% of general technologies and structural components can reuse mature technologies, thereby reducing R&D costs and shortening the R&D cycle.
Meanwhile, the deep application of artificial intelligence and digital simulation technology in R&D and design further accelerates product iteration; the company has a deep partnership with leading downstream wafer foundries, and customers’ willingness to introduce new products continues to increase, effectively shortening the equipment verification and mass production cycle.
Yin Zhiyao further stated that the company's dielectric etching products continue to maintain rapid growth, and the next-generation 90:1 ultra-high aspect ratio low-temperature etching equipment has been delivered to clients for verification. Currently, the company has fully covered various ultra-high aspect ratio process requirements for memory etching, and its technical strength continues to benchmark against international leading levels.
While consolidating its leading position in the etching business, AMEC continues to improve its product portfolio. In terms of thin film equipment , it has successfully developed tungsten series thin film deposition equipment, ALD titanium nitride, ALD titanium aluminum, ALD tantalum nitride and other products, as well as molybdenum metal deposition equipment.
Yin Zhiyao revealed that the company's PECVD equipment, which uses a very high frequency decoupled reactive ion plasma source and is equipped with 16 reaction stages, is progressing smoothly with various verification efforts from customers. The newly developed CuBS PVD multi-reaction-cavity integrated equipment significantly reduces the resistivity of BS compared to standard equipment at home and abroad, and increases the output rate by 50% to 100%. It has been recognized by several leading customers and has been delivered to advanced logic device R&D lines in China for verification.
The company is currently simultaneously advancing the development of more than 20 new equipment in six major categories. At present, it has launched a full range of thin film equipment products, including LPCVD, ALD, EPI, PVD CuBS, and PECVD. Many LPCVD and ALD equipment adapted to advanced logic and advanced memory processes have been commercialized and delivered; the etching equipment has achieved full coverage of process nodes from 65 nm to 3 nm and more.
When discussing the accelerated development of new products, Yin Zhiyao told the reporter from Science and Technology Innovation Board Daily that the company has achieved modularization and maturation of core technologies. New product development only requires the targeted development of 30%-40% of customized modules, while the remaining 60%-70% of general technologies and structural components can reuse mature technologies, thereby reducing R&D costs and shortening the R&D cycle.
Meanwhile, the deep application of artificial intelligence and digital simulation technology in R&D and design further accelerates product iteration; the company has a deep partnership with leading downstream wafer foundries, and customers’ willingness to introduce new products continues to increase, effectively shortening the equipment verification and mass production cycle.
Zhengzhou University announces new research results on diamond MOSFETs.
A team led by Professor Shan Chongxin at Zhengzhou University has identified a key bottleneck in next-generation semiconductor technology: abnormal drift in the performance of hydrogen-terminated diamond metal-oxide-semiconductor field-effect transistors (H-diamond MOSFETs). Published in Diamond & Related Materials, their study reveals that these ultra-high-performance devices capable of handling voltages over 2000 V and GHz frequencies are limited by "trapping effects" within the gate dielectric. The research demonstrates that while H-diamond MOSFETs show exceptional potential for extreme-environment electronics, their transfer curves exhibit significant instability during short-term testing due to hole trapping by defects in the aluminum oxide (Al₂O₃) layer. By analyzing capacitance-voltage (CV), pulse IV, and transient current data, the team successfully mapped the time constants and spatial distribution of these traps, offering a roadmap to improve device reliability through interface defect reduction.
The findings from Zhengzhou University represent a pivotal step toward transforming diamond semiconductors from laboratory curiosities into practical solutions for high-power, high-frequency applications. While existing research has largely focused on Al₂O₃/diamond interface states in isolation, this work provides the first systematic analysis of trap response mechanisms across the entire MOS structure, clarifying why device performance degrades under dynamic stress. The researchers conclude that mitigating surface adsorbates and lowering defect densities at critical interfaces can eliminate hysteresis and drift, unlocking the full potential of diamond materials for aerospace, automotive, and energy sectors where silicon-based chips fail. This analytical framework not only addresses a long-standing technical hurdle but also supplies essential data required to accelerate the transition of H-diamond devices from experimental prototypes to industrial deployment.
A semiconductor advanced ceramics project with an investment of 1 billion yuan has been launched in Kunshan!
According to China Powder Network , Suzhou Zhongxinlian Electronic Materials Co., Ltd. recently held a groundbreaking ceremony for its semiconductor advanced materials and core component manufacturing base project . The project represents a total investment of 1 billion yuan. Upon completion and reaching full production capacity, it is expected to produce 104,000 ceramic structural parts and 26,000 weld-processed parts annually. Core product categories include key structural components such as electrostatic chucks and advanced ceramics for etching equipment. Simultaneously, the company will use this opportunity to further increase its production capacity, optimize its product structure, and enhance its core competitiveness, contributing to a new level of domestic production of semiconductor core materials in China.
Suzhou Zhongxinlian Electronic Materials Co., Ltd. was established in February 2020. The company focuses on the manufacturing of semiconductor chips using processes below 14 nanometers, specializing in the research and development and production of advanced ceramic materials for plasma etching equipment. Its core products revolve around yttrium oxide-based ceramic materials, encompassing high-purity yttrium oxide ceramic structural components and yttrium oxide/alumina composite YAG ceramic structural components. It also provides yttrium oxide and dense coating sputtering services for various substrate components used in plasma etching equipment. Its products hold the number one market share in electrostatic chucks used in LCD panel etching processes, and its electrostatic chucks for semiconductors have achieved mass production after breaking through key technologies, solving a bottleneck problem in this field.
In the field of yttrium oxide-related ceramic structural components, the company has successfully overcome technical challenges in key aspects such as powder mixing and granulation, green body forming, green body processing, atmosphere sintering, precision machining, and precision cleaning through independent research and development. This enables the company to provide high-specification, high-quality, and high-stability yttrium oxide-related ceramic structural components for semiconductor devices.
Suzhou Zhongxinlian Electronic Materials Co., Ltd. was established in February 2020. The company focuses on the manufacturing of semiconductor chips using processes below 14 nanometers, specializing in the research and development and production of advanced ceramic materials for plasma etching equipment. Its core products revolve around yttrium oxide-based ceramic materials, encompassing high-purity yttrium oxide ceramic structural components and yttrium oxide/alumina composite YAG ceramic structural components. It also provides yttrium oxide and dense coating sputtering services for various substrate components used in plasma etching equipment. Its products hold the number one market share in electrostatic chucks used in LCD panel etching processes, and its electrostatic chucks for semiconductors have achieved mass production after breaking through key technologies, solving a bottleneck problem in this field.
In the field of yttrium oxide-related ceramic structural components, the company has successfully overcome technical challenges in key aspects such as powder mixing and granulation, green body forming, green body processing, atmosphere sintering, precision machining, and precision cleaning through independent research and development. This enables the company to provide high-specification, high-quality, and high-stability yttrium oxide-related ceramic structural components for semiconductor devices.
SiCC is part of China's growing Silicon Carbide wafer producers. It had 51% of 8-inch substrate market in 2025, but is still losing money. Will the rising demand from AI DCs change this?
Xinhuazhang Proposes a "Closed-Loop Evidence" Framework for Chip-Verified Intelligent Agents
At DVCon China 2026, Professor Xu Qiang, Chief Scientist of Xinhuazhang, delivered a keynote speech introducing a groundbreaking "Closed-Loop Evidence" framework for chip verification intelligent agents. He emphasized that the true value of AI Agents in electronic design automation (EDA) lies not in their ability to generate RTL code, test cases, or debugging hypotheses, but in transforming these outputs into verifiable, traceable, and governable engineering evidence. As generative AI integrates into chip development, the industry faces a critical challenge: bridging the gap between the probabilistic nature of large language models and the deterministic, evidence-based requirements of hardware verification.
To address this, Xinhuazhang proposes three foundational pillars for building trustworthy verification agents. First, verification semantic mapping converts natural language requirements into structured, executable verification objectives while treating AI outputs as "candidate hypotheses" requiring EDA tool validation. Second, EDA engine evidence-driven reasoning ensures that assertions, coverage interpretations, or debugging proposals are substantiated by simulation, formal verification, or regression results before entering the trusted workflow. Third, a governable control plane establishes clear boundaries for agent autonomy defining which actions require human approval, audit trails, or risk classification ensuring that intelligent assistance remains auditable and engineering-compliant.
Professor Xu stressed that EDA-native capabilities form a critical barrier to entry for trusted verification agents. Unlike generic AI tools, industrial-grade agents must deeply integrate with simulation engines, formal verification infrastructure, debugging workflows, and approval processes. Xinhuazhang's expertise in digital verification provides the foundation for this evidence-centric approach, where AI Agents operate as embedded collaborators within real verification workflows rather than external chat interfaces. Early internal pilots demonstrate promising results: Formal Agents achieved over 10x efficiency gains in protocol compliance tasks with 95%+ proof coverage, while Simulator/Debug Agents improved coverage convergence and fault localization across multiple SoC modules.
Importantly, this framework redefines rather than replaces the role of verification engineers. As agents handle generation, execution, and preliminary analysis, engineers evolve into managers of verification intent, assessors of risk boundaries, and final adjudicators of evidence quality. Professor Xu affirmed that "verification engineers in the AI era will not be replaced, but amplified." This vision aligns with Xinhuazhang's EDA 2.0 strategy: advancing an open, intelligent, and platform-based pathway that shifts verification from tool-driven automation to evidence-driven, trusted human-AI collaboration—ultimately helping chip developers enhance R&D efficiency without compromising verification quality, engineering controllability, or signature-level credibility.
To address this, Xinhuazhang proposes three foundational pillars for building trustworthy verification agents. First, verification semantic mapping converts natural language requirements into structured, executable verification objectives while treating AI outputs as "candidate hypotheses" requiring EDA tool validation. Second, EDA engine evidence-driven reasoning ensures that assertions, coverage interpretations, or debugging proposals are substantiated by simulation, formal verification, or regression results before entering the trusted workflow. Third, a governable control plane establishes clear boundaries for agent autonomy defining which actions require human approval, audit trails, or risk classification ensuring that intelligent assistance remains auditable and engineering-compliant.
Professor Xu stressed that EDA-native capabilities form a critical barrier to entry for trusted verification agents. Unlike generic AI tools, industrial-grade agents must deeply integrate with simulation engines, formal verification infrastructure, debugging workflows, and approval processes. Xinhuazhang's expertise in digital verification provides the foundation for this evidence-centric approach, where AI Agents operate as embedded collaborators within real verification workflows rather than external chat interfaces. Early internal pilots demonstrate promising results: Formal Agents achieved over 10x efficiency gains in protocol compliance tasks with 95%+ proof coverage, while Simulator/Debug Agents improved coverage convergence and fault localization across multiple SoC modules.
Importantly, this framework redefines rather than replaces the role of verification engineers. As agents handle generation, execution, and preliminary analysis, engineers evolve into managers of verification intent, assessors of risk boundaries, and final adjudicators of evidence quality. Professor Xu affirmed that "verification engineers in the AI era will not be replaced, but amplified." This vision aligns with Xinhuazhang's EDA 2.0 strategy: advancing an open, intelligent, and platform-based pathway that shifts verification from tool-driven automation to evidence-driven, trusted human-AI collaboration—ultimately helping chip developers enhance R&D efficiency without compromising verification quality, engineering controllability, or signature-level credibility.