Chinese semiconductor thread II
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Tianren Micro-Nano showcases its innovative nanoimprint technology at SPIE AR|VR|MR, demonstrating its leading advantages in micro-nano manufacturing.
At the recently concluded SPIE AR|VR|MR exhibition, Tenren Micro-Nano, a leading domestic provider of nanoimprint lithography equipment, became the focus of the exhibition with its cutting-edge technological achievements and one-stop solutions, fully demonstrating the strong strength of Chinese enterprises in the field of micro-nano optical manufacturing.
During the exhibition, Tenren Micro-Nano showcased its high-precision nanoimprint lithography equipment and processes for augmented reality, virtual reality, and mixed reality applications. Their exhibited nanoimprint lithography system can achieve nanometer-level resolution and high aspect ratio structure replication, making it particularly suitable for the large-scale production of micro- and nanostructures such as AR waveguide diffraction gratings, microlens arrays, and nanopores. Their 310mm square fully automated nanoimprint lithography production line not only meets the stringent requirements of next-generation display optics for precision, consistency, and mass production capabilities, but also boasts significant advantages in cost control and production efficiency.
The technical expert team from Tianren Micro-Nano engaged in in-depth technical exchanges with leading AR/VR companies, top research institutions, and industry experts from around the world. The company showcased its one-stop service capabilities, from equipment R&D and process development to mass production support, which received high praise from the professional attendees.
This participation in the exhibition further solidified Tenren Micro-Nano's brand influence in the global micro-nano manufacturing field. The company stated that it will continue to increase its R&D investment, taking independent innovation as the core driving force, and is committed to providing more competitive micro-nano optical manufacturing solutions for the AR/VR/MR industry.
A team led by Qiu Chenguang and Peng Lianmao from the School of Electronic Engineering at Peking University has developed the world's lowest power ferroelectric transistor.
Peking University has made a breakthrough in the field of non-volatile memory. The team led by Qiu Chenguang and Peng Lianmao from the School of Electronic Engineering has proposed the first "nanogate ferroelectric transistor with ultralow operating voltage of 0.6 V". By ingeniously designing the device structure of ferroelectric memory and introducing the nanogate electric field convergence enhancement effect, the team developed a ferroelectric transistor that can operate at an ultra-low voltage of 0.6 V, reducing energy consumption to 0.45 fJ/μm. Furthermore, they reduced the physical gate length to the 1-nanometer limit, making it the smallest and lowest-power ferroelectric transistor internationally to date. This provides a more promising new physical mechanism memory device for building high-performance sub-1-nanometer node chips and high-computing-power AI chip architectures. This groundbreaking achievement, titled "Nanogate ferroelectric transistors with ultralow operating voltage of 0.6 V", was published online in the Science sub-journal *Science Advances*.
Logic devices and memory devices are the two fundamental components in building integrated circuits. Logic units constitute the "computation and control center" of a chip, while memory units constitute its "data warehouse," together accounting for over 70% of the integrated circuit market. Driven by Moore's Law, logic transistors have continuously improved in performance through process miniaturization and architectural iteration. Currently, the industry has achieved mass production of 2-nanometer node logic chips, and CMOS transistors operate at a low voltage of 0.7V. However, in contrast, the performance development of non-volatile memory has lagged behind for decades, and mainstream non-volatile Flash memory technology is difficult to miniaturize to advanced nodes. Most importantly, Flash memory requires high voltages above 5V for data erasure and writing. Therefore, existing chips must integrate buck-boost circuits between logic units and non-volatile memory to complete the operating voltage conversion, which brings a series of problems such as additional area overhead and increased power consumption. More importantly, the core of modern AI chip architecture lies in data flow optimization. Voltage mismatch between logic and memory directly leads to poor data interaction, severely hindering the computing power of AI chips and significantly increasing power consumption.
Logic devices and memory devices are the two fundamental components in building integrated circuits. Logic units constitute the "computation and control center" of a chip, while memory units constitute its "data warehouse," together accounting for over 70% of the integrated circuit market. Driven by Moore's Law, logic transistors have continuously improved in performance through process miniaturization and architectural iteration. Currently, the industry has achieved mass production of 2-nanometer node logic chips, and CMOS transistors operate at a low voltage of 0.7V. However, in contrast, the performance development of non-volatile memory has lagged behind for decades, and mainstream non-volatile Flash memory technology is difficult to miniaturize to advanced nodes. Most importantly, Flash memory requires high voltages above 5V for data erasure and writing. Therefore, existing chips must integrate buck-boost circuits between logic units and non-volatile memory to complete the operating voltage conversion, which brings a series of problems such as additional area overhead and increased power consumption. More importantly, the core of modern AI chip architecture lies in data flow optimization. Voltage mismatch between logic and memory directly leads to poor data interaction, severely hindering the computing power of AI chips and significantly increasing power consumption.
Novel picometer heterodyne interferometer for metrology
Directly traceable ultra-precision displacement metrology: a heterodyne self-traceable grating interferometer
Abstract
The heterodyne grating interferometer, renowned for its superior resolution and robust environmental adaptability, is suitable for high-speed, ultra-precise displacement measurement and has been widely researched and applied. The heterodyne grating interferometer employs the grating pitch as its measurement reference. However, due to the lack of direct traceability for the grating pitch and the accumulation of errors during length measurement transfer in calibration, the accuracy, consistency, and comparability of displacement measurements are diminished. Self-traceable gratings (STG) fabricated using atomic lithography technology, whose pitch is directly traceable to the chromium atomic transition frequency, exhibit a line density of 4700 lines/mm with picometre-level accuracy and uniformity. Therefore, this paper proposes what we believe to be a novel approach for developing a heterodyne self-traceable grating interferometer (He-STGI) based on STG, which combines stable, ultra-high-precision heterodyne interferometric length metrology with intrinsically traceable displacement readout. Experimental results show excellent agreement with a traceable iodine-stabilized laser interferometer (IS-LI), demonstrating 2-nm-level resolution, a 1.23 nm standard deviation over a 2-min static record, and a ∼0.5 nm deviation in dynamic displacement repeatability. The proposed He-STGI provides a novel solution for ultra-precision displacement metrology and enables a shortened and simplified traceability chain for displacement calibration.
High-Power and Fiber-Solid Hybrid MOPA Nanosecond Laser for High-Efficiency 4H-SiC Wafers Slicing
Abstract
Laser slicing of 4H-SiC wafers offers high efficiency and minimal material loss. While nanosecond lasers are the preferred light source, simultaneously achieving high output power, excellent beam quality (M2 < 1.3), and broad operational tunability remains an outstanding challenge. This study developed a highly efficient nanosecond laser source using hybrid fiber and solid-state multi-stage amplification architecture. With excellent beam quality (M2 < 1.3), it achieves the highest output power, widest continuously tunable pulse width range, and broadest repetition rate range currently reported for 4H-SiC laser slicing. This advancement is poised to advance the continued development of 4H-SiC slicing technology.
Shenzhen's new "AI+" policy: Strengthening the semiconductor industry by focusing on AI chips.
On February 9, 2026, the Shenzhen Municipal Bureau of Industry and Information Technology issued the "Shenzhen Action Plan for Advanced Manufacturing Industry with 'Artificial Intelligence+' (2026-2027)." The plan aims to accelerate new industrialization by deeply integrating AI technology into the manufacturing sector.
Key Strategic Goals (By 2027) The plan targets a development pattern of "One Base, One Center, One Alliance, 100 Scenarios, and Multiple Applications," specifically:
Key Strategic Goals (By 2027) The plan targets a development pattern of "One Base, One Center, One Alliance, 100 Scenarios, and Multiple Applications," specifically:
- Establishing a national pilot base for AI applications (consumer mobile terminal direction).
- Building an industrial intelligent body innovation center.
- Forming an industrial knowledge alliance.
- Opening 100 application scenarios and promoting 100 demonstration applications.
Focus on Semiconductors and Integrated Circuits A core pillar of the policy is empowering the semiconductor industry through AI:
- Process Optimization: Utilizing AI to improve efficiency in chip design and software coding.
- AI Chip Development: Focusing on high-performance, energy-efficient dedicated SoC chips for AI terminals (smartphones, glasses, robots) and supporting new architectures like in-memory computing.
- Automotive Substitution: Targeting the new energy vehicle market by supporting the domestic substitution of 14nm and below automotive-grade chips, including intelligent driving AI chips, cockpit SoCs, and domain controllers.
Empowerment of Other Key Industries The Action Plan outlines AI integration strategies for several other sectors:
- Electronic Information: R&D of AI mobile phones, glasses, and smart screens.
- Automobile: "Vehicle-road-cloud integration" and intelligent manufacturing.
- Robots: Developing embodied intelligence and multimodal interaction models.
- Low-Altitude Economy: Autonomous UAV systems and intelligent airspace management.
- Medicine: AI-driven drug discovery and medical device innovation.
- Traditional Industries: Upgrading sectors like clothing, jewelry, and furniture via generative AI design and flexible production.
Support Measures To ensure implementation, Shenzhen will:
- Strengthen Policy & Finance: Increase financial support and encourage "challenge-based" enterprise participation.
- Open Scenarios: Establish application scenario open centers and release demand lists to match supply and demand.
- Training & Promotion:
Incredible the level of cooperation between Chinese companies and Universities.
Industrial-Grade Differential Interference Contrast Inspection System for Unpatterned Wafers.
Skyverse Technology Co., Ltd.School of Mechanical Engineering, Xi’an Jiaotong University.
Abstract
In the field of optical inspection for unpatterned wafer surfaces, this paper presents a novel inspection system designed to meet the semiconductor industry’s growing demand for high efficiency and cost-effectiveness. The system is built around the principles of simplicity, stability, speed, and low cost. Its core is a low-speed stepping rotary line-scan architecture. This architecture is integrated with a two-step phase-shifting algorithm. The combination leverages line-scan differential interference contrast (DIC) technology. This aims to transform DIC technology—traditionally used for detailed observation—into an industrialized solution capable of rapid, accurate quantitative measurement. Experimental validation on an equivalent platform confirms strong performance. The system achieves an imaging uniformity exceeding 85% across dual channels. Its Modulation Transfer Function (MTF) value is greater than 0.55 at 71.8 lp/mm. The vertical detection clearly resolves 3 nm standard height steps. Additionally, the throughput exceeds 80 wafers per hour. The proposed line-scan DIC system achieves both high inspection accuracy and industrial-grade scanning speed, delivering robust performance and reliable operation.
Skyverse is a top tier Chinese metrology tools manufacturer.
their new 130,000 sqm production plant currently under construction. this base will manufacturer metrology tools for advanced nodes.
Apple: where can I get some of that alleged overcapacity of cheap memory?
On a serious note, didn't US lawmakers pressure Apple to cut YMTC as a memory supplier a few years ago on national security grounds? Oh how the times have changed...
I really hope that the government put limits on how many memory US companies can buy, so the domestic supply doesn't dry up. After all this is a problem of their own making. Letting US AI companies to buy unpatterned wafer supply to limit competition and delaying CXMT and YMTC capacity build up.