Zhaoxin KH-50000 processor makes its physical debut, and the domestically produced computing power base has reached the same level as international flagships
The 2025 China International Communications Exhibition (PT Exhibition) opened grandly in Beijing. Hailed as a barometer of communications industry development and a bellwether of technological evolution, the PT Exhibition serves as a vital window into the latest developments in the information and communications industry.
At this year's exhibition, Zhaoxin's new Kaisheng KH-50000 server processor made its physical debut. It uses an LGA package with dimensions of 72 x 76mm, a step up from the previous-generation KH-40000 processor (56.5 x 77.5mm).

The Kaisheng KH-50000 utilizes a chiplet architecture, significantly improving computing density. It supports up to 96 CPU cores per socket and features a 384MB cache. This represents a 200% increase in core count compared to the previous-generation KH-40000 (32 cores), bringing its single-socket performance density close to that of the AMD EPYC 9755 (128 cores/512MB cache) . The CPU can reach a clock speed of 2.2 to 3.0GHz.
In addition, Kaisheng KH-50000 has also fully upgraded its IO interface, supporting up to 12 channels of DDR5 ECC memory, 128 channels of PCIe 5.0/ZPI/CXL and 16 channels of PCle 4.0/SATA/USB and other mainstream IO, supporting dual-channel and quad-channel interconnection , achieving greater data bandwidth, lower latency and power consumption.
Kaisheng KH-50000 processor can be used for computing platforms such as workstations, general-purpose servers, high-density AI servers, and high-density storage servers, and can provide a stronger hardware foundation for complex computing scenarios.