High-performance thin-film transistor (TFT) devices with high on-off ratio and low subthreshold swing are the key technology for developing a new generation of large-area high-definition display, flexible electronics / sensing and brain-computer interface applications. Among them, ultra-fine and ultra-short crystalline silicon nanowire channels have become ideal structures for building high-performance TFT devices due to their good gate control and large current driving capabilities. Although such fine channel structures have become mainstream in the process of "micro" electronic devices, they rely on ultra-high precision deep ultraviolet / extreme ultraviolet lithography (D/EUV) and etching technology on silicon wafers, so they cannot be applied on large-size glass or polymer substrates of large-area "macro" electronic devices. How to integrate and prepare fine nanochannels with a diameter of less than 30 nm and a length of less than 100 nm based on limited thermal budget (<500℃) and low lithography accuracy (>1.5 μm) has become a key technical bottleneck faced by the development of a new generation of high-performance TFT devices.
In response to this challenge, Professor Yu Linwei, Professor Wang Junzhuan of Nanjing University and Teacher Hu Ruijin of Yangzhou University, based on the independently innovative in-plane solid - liquid - solid (IPSLS) nanowire growth mode, proposed for the first time to use the catalytic "droplet step-jump" growth dynamics to successfully achieve reliable integrated preparation of ultra-fine and ultra-short crystalline silicon nanowire channel arrays. Specifically, based on the low-temperature positioning growth (<350℃) capability of the IPSLS growth mode , the catalytic droplets are precisely guided to grow to the edge of the jumping cross-step, and by controlling the " Step-Necking contraction" effect of the flexible droplets crossing the steps, the required Thick (45nm)/Thin (25nm)/Thick (45nm) ultra-fine channel structure is grown in one step at the edge of the step, where the ultra-fine channel length is only Lg~90 nm , and the thick wires at both ends provide natural ideal S/D contacts - completely similar to the ideal channel and S/D contact architecture in advanced fin-gate transistors (Fin-FETs) .
Figure 1 The principle and process of necking growth of silicon nanowire arrays as well as the morphology of silicon nanowire arrays and their diameter statistics.
Benefiting from this, Step-Necking nanowire TFT devices have demonstrated excellent gate control effects and greatly improved transport characteristics, achieving a high-performance transistor TFT device with a high switching ratio of 8×10 7 and a subthreshold swing of only SS=70 mV/dec . Based on the fine channel preparation strategy brought about by this "droplet step", the micro-nano device structure and excellent transport characteristics of the most cutting-edge "microelectronic" devices can be "directly implanted" into the large-area "macroelectronic" field, opening up a new path for the integrated preparation technology of high-performance crystalline silicon devices to create a new generation of high-performance display drive logic, flexible sensing and brain-computer interfaces and other emerging applications!
