Chinese semiconductor thread II

[tphuang]

50k wpm is a lot



Doing some rough calculation here. I think 500k Ascend chips is a lot. I did some calculation assuming they are making Ascend-920 (and computation increases to 600 TFLOPS FP16), that'd be 300 EFLOPS a year, which is way more than what they are adding right now

Server chips being 3x that seems reasonable
10 million desktop a year would easily dominate the market (I maybe overestimating things there)

The biggest load (by far) are the kirin chips for phones and tablets and possibly the new vision pro products.

I put down 150 million for all of that, which again is a very high number. That resulted in 30k wpm for the kirin SoCs

if they can get to 50k wpm, they can supply chips to other OEMs also.

50k wpm even if we assume 400 chips per wafer is 240 million per year.

to support the entire Chinese phone OEM market, you need about 100k wpm

 

[Totoro]

Is there any statistic about overall number of semiconductor units made in China through the years? 2023, 2022 and earlier?

 

[gelgoog]

market is shifting upward to 28-55nm segment
...
They want to add 40-50k 12-inch wafer capacity per year (about 100k 8-inch), but are actually spending enough capex for 100k 12-inch of 28 to 90nm (see their Jincheng & Tianjin plant both budgeted 7.5B capex for 100k).

SMIC is not competitive with Nexchip for DDICs in larger processes. Nexchip uses 300mm wafers to make 55nm and larger chips.
SMIC only has the B1 fab in Beijing with that kind of setup. But it has much lower capacity. Half or less. Most of SMIC's fabs which make chips up to 55nm use 200mm wafers. Since Hua Hong's Wuxi fab also has 300mm wafers to make 55nm and larger the competition is brutal.
The main advantage SMIC has left is that its fabs, unlike Nexchip and Hua Hong, are likely fully depreciated at this point. Which means they can operate them with just marginal profits without bleeding red ink. Nexchip and Hua Hong are basically in a blood bath. It will be hard to justify the cost of building these fabs for older processes.

This is why Liang Mong Song's idea of continuing to push the leading edge nodes at SMIC makes sense really.

Nexchip also began producing 40nm and will eventually do 28nm as well. This will make it harder for SMIC to find as many users of its brand new 28nm fabs. At least for DDICs. But unlike Nexchip or Hua Hong if things go sour then SMIC can just move those fabs to FinFET production.

I would not be surprised if SMIC also eventually develops some sort of intermediate process node to better utilize capacity at fabs which cannot produce 14nm FinFET. This could be a 22nm planar process, or it could be some sort of larger FinFET. You have to remember that Intel was the first to use FinFET, but they did it at 22nm node, aka "tri-gate" to improve power consumption. This would enable higher density and lower power consumption than 28nm planar while still using the same tools. And the tools to make this process wouldn't fall under current US sanctions which are for manufacturing at 16nm or lower.

The biggest load (by far) are the kirin chips for phones and tablets and possibly the new vision pro products.
...
to support the entire Chinese phone OEM market, you need about 100k wpm

Huawei can just better segment their SoCs. The smartphone SoCs don't need to all be Kirin 9000S. Do you really need AI blocks on all the SoCs? Can't you just run the AI code on the GPGPU on lower end phones? Do you really need to put the 5G modem in the same chip? Shouldn't you just put the modem as a separate chiplet? This would allow mixing and matching different modems and main processors. You could use a lower resolution process on the modem as well.

 

[FairAndUnbiased]

Peking University develops vibration characteristics etching control equipment for MEMS sensors based on ultra-short pulse laser​

Recently, the research team of the School of Integrated Circuits of Peking University, the National Key Laboratory of Micron and Nano Processing Technology, and the Advanced Innovation Center of Integrated Circuits published "Automatic Pico Laser Trimming System" in the "IEEE Transactions on Semiconductor Manufacturing " journal. for Silicon MEMS Resonant Devices based on Image Recognition" article was awarded the journal's 2023 Best Paper Honor Award (1-3 articles/year). The first author of the paper is Liu Yuxian, a 2019 doctoral candidate in the School of Integrated Circuits, Peking University (supervisor: Professor Zhang Dacheng). The corresponding author is Senior Engineer Cui Jian of Peking University. The co-authors include Professor Zhang Dacheng and Senior Engineer Zhao Qianchengzheng.

Silicon micromachined sensor (MEMS) chips have remarkable characteristics such as small size, low cost, strong environmental adaptability, and easy mass manufacturing. They have become key core devices in important industries such as aerospace, communication electronics, and automotive electronics. The relative error of the MEMS chip microstructure process is large, which brings about asymmetry in its mechanical characteristic parameters, causing the accuracy of the MEMS sensor to degrade and affecting the batch production yield. Currently, the industry still lacks complete error analysis and wafer-level control solutions that are universal, intelligent, and efficient, which has become an industry 'pain point' that needs to be solved in the field of high-end MEMS sensor devices.

In response to the above problems and needs, the Peking University research team carried out the research and development of silicon micro-sensor vibration characteristics etching control equipment based on ultra-short pulse laser, and completed an ultra-short pulse laser light source system, laser optical path system, and three-dimensional precision mobile platform system. , design, debugging and verification of hardware and software algorithms such as CCD image recognition system, sensitive structural mechanical characteristic parameter online identification system and processing residue processing system.

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This is mask free, resist free lithography. Interesting. Ultrashort laser actually must be mask free as the pulse has a broad spectrum in the frequency domain, making interference patterns much more complex than monochromatic light.

Feature size will probably be closer to micron scale, and write speed will be slow since it's sequential. So this looks like something that's suitable for mask production or a short run of very complex MEMS rather than wafers full of commodity MEMS.

 

[tphuang]

SMIC is not competitive with Nexchip for DDICs in larger processes. Nexchip uses 300mm wafers to make 55nm and larger chips.
SMIC only has the B1 fab in Beijing with that kind of setup. But it has much lower capacity. Half or less. Most of SMIC's fabs which make chips up to 55nm use 200mm wafers. Since Hua Hong's Wuxi fab also has 300mm wafers to make 55nm and larger the competition is brutal.
The main advantage SMIC has left is that its fabs, unlike Nexchip and Hua Hong, are likely fully depreciated at this point. Which means they can operate them with just marginal profits without bleeding red ink. Nexchip and Hua Hong are basically in a blood bath. It will be hard to justify the cost of building these fabs for older processes.

This is why Liang Mong Song's idea of continuing to push the leading edge nodes at SMIC makes sense really.

Nexchip also began producing 40nm and will eventually do 28nm as well. This will make it harder for SMIC to find as many users of its brand new 28nm fabs. At least for DDICs. But unlike Nexchip or Hua Hong if things go sour then SMIC can just move those fabs to FinFET production.

btw, SMIC has added a lot of 40 and 55nm capacity in their new Jingcheng and Shenzhen fabs recently. And it seems like a lot of that should be for DDIC. So, I would caution saying they are not competitive vs Nexchip

 

[gelgoog]

btw, SMIC has added a lot of 40 and 55nm capacity in their new Jingcheng and Shenzhen fabs recently. And it seems like a lot of that should be for DDIC. So, I would caution saying they are not competitive vs Nexchip

Aren't those supposed to be 28nm fabs? I guess they could make chips at 40nm as well but it wouldn't use the capacity quite as well.

 

[tphuang]

Aren't those supposed to be 28nm fabs? I guess they could make chips at 40nm as well but it wouldn't use the capacity quite as well.

no, they were advertised as 28-90 or even 28-180nm in the case of Tianjin. In earnings call, they are pretty explicit in saying that they are adding capacity across 28, 40 and 55nm. Even 65nm was constrained 2 quarters ago, but they added some capacity for it and that's no longer an issue.

For example, they are only at 55nm for BCD right now. The demand for that is pretty high

 

[tokenanalyst]

Is there any statistic about overall number of semiconductor units made in China through the years? 2023, 2022 and earlier?

China Bureau of Statistics?

 

[LanceD23]

The weird field of computational lithography.

I think this is the difference maker.
Why TSMC doesn't do computational lithography with DUV? Well because layout isn't done by TSMC only the design company do layout. And it's alot of work, and many design companies aren't willing to put in the work. Huawei has No choice.

alot of western folks guessing its only using multipattern on 7nm or 5nm, and becomes prohibitively expensive as yield suffer from too many patterns,

I think SMIC only use1 or 2 patterns to control cost and Huawei is taking care of corrective layouts.

Maybe theoretically China doesn't need EUV. SMIC claiming its working on 3nm DUV and if it works then urgency of EUV is overhyped.

Here, I am predicting EUV is Not needed in China in foreseeable future..

No wonder Huawei is so confident nowadays.

 

[tokenanalyst]

China already have a 28nm wafer fabrication facility completely domestic already running for a year or even a few years.

Patterning process tool chain:

OPC- Computational lithography: DJEL/others
Lithography: SMEE SSX-800
Coating/developing: KingSemi Immersion track
ADI: SMEE
Etching: AMEC/NAURA
AEI: SMEE
CD-SEM: DJEL/others

This has been running in a feedback loop for while.

too crazy?