Chinese semiconductor thread II

OptimusLion

New Member
Registered Member
On December 24, Zhejiang Xingyao Semiconductor Co., Ltd. held a 5G RF filter chip wafer production line project commissioning ceremony in Wenzhou Bay New District and Longwan District, marking a milestone for Xingyao Semiconductor from fabless to IDM. The total investment of the project is 750 million yuan, and it is expected to achieve an annual output of 120,000 high-performance RF filter wafers after it goes into production.

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sunnymaxi

Major
Registered Member
This is mind-boggling..

The University of Hong Kong has developed a revolutionary diamond preparation technology that produces 2-inch diamond wafers in 10 seconds​


on December 24 that the Faculty of Engineering of the University of Hong Kong, in collaboration with the Southern University of Science and Technology and Peking University, has successfully developed a breakthrough "edge exposure stripping" technology that can quickly mass-produce large-size ultra-thin, ultra-flexible diamond films.

Moreover, the technology is compatible with existing semiconductor manufacturing technology and can be used to manufacture various electronic, photonic, mechanical, acoustic and quantum devices.

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gelgoog

Lieutenant General
Registered Member
Regarding the U.S.’s ongoing restrictions on China’s semiconductor development, including the export ban on EUV lithography machines, Fouquet stated that prohibiting the export of these machines to China would cause the country’s semiconductor industry to lag 10 to 15 years. He noted that the ban is indeed effective, according to the report.
China is like 4 years behind the leader in process technology. TSMC N5 came out in 2020.
The rest is guesstimates.

SMIC introduced N+2 in 2021, while TSMC introduced N7+ in 2019. Both have similar density.
Back then you could argue the difference was closer to 2 years behind. Although even back then SMIC had worse yields than TSMC. So maybe 3 years would be more accurate.

It is still to early to tell, but I think a lag of 10 or 15 years is just plain bullshit. Too many smart minds, and too much money in China. They will figure out a way out of the bind the combined West led by the US put them into. One relatively simple answer is just to go vertical and add more layers. This is already the case in NAND (V-NAND), is likely to become the case in DRAM (3D-DRAM), and could also be applied to logic.

For example in logic you could add backside power delivery like Intel is doing with 18A so that the power traces are in a separate layer and don't take up space in the main layers. You could also have multiple layers with transistors. And you could add CVD diamond layers in between the transistor layers to dissipate the heat. The diamond heat dissipation layers would be connected via diamond pillars (TSV).

Alternatively, as a simpler solution, you can take advantage of the fact that a huge chunk of the die area in a modern SoC is cache. So you add all the L2 and L3 cache in a separate layer connected to the logic layers with TSV similar to AMD's 3D V-cache. This way the logic layers can have more transistors.

Then you have the issue of throughput. i.e. that TSMC can "stamp" more transistors per unit of time than say SMIC can. The answer to that can be larger masks and larger wafers.
 
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staplez

New Member
Registered Member
China is like 4 years behind the leader in process technology. TSMC N5 came out in 2020.
The rest is guesstimates.

SMIC introduced N+2 in 2021, while TSMC introduced N7+ in 2019. Both have similar density.
Back then you could argue the difference was closer to 2 years behind. Although even back then SMIC had worse yields than TSMC. So maybe 3 years would be more accurate.

It is still to early to tell, but I think a lag of 10 or 15 years is just plain bullshit. Too many smart minds, and too much money in China. They will figure out a way out of the bind the combined West led by the US put them into. One relatively simple answer is just to go vertical and add more layers. This is already the case in NAND (V-NAND), is likely to become the case in DRAM (3D-DRAM), and could also be applied to logic.

For example in logic you could add backside power delivery like Intel is doing with 18A so that the power traces are in a separate layer and don't take up space in the main layers. You could also have multiple layers with transistors. And you could add CVD diamond layers in between the transistor layers to dissipate the heat. The diamond heat dissipation layers would be connected via diamond pillars (TSV).

Alternatively, as a simpler solution, you can take advantage of the fact that a huge chunk of the die area in a modern SoC is cache. So you add all the L2 and L3 cache in a separate layer connected to the logic layers with TSV similar to AMD's 3D V-cache. This way the logic layers can have more transistors.

Then you have the issue of throughput. i.e. that TSMC can "stamp" more transistors per unit of time than say SMIC can. The answer to that can be larger masks and larger wafers.
I think he's only talking about lithography technology. But what that means is important. The first EUV machine was installed in 2010. If as we estimate, China will have its first EUV machine in 2025. That makes his statement exactly correct. However it also reveals that China's immersion DUVs are already close to ASMLs. I've always had a suspicion that ASML knows more about Chinese lithography than even we know. His statement makes me believe that SMEE's lithography machine is already in use as we all suspected. We have to remember the source of the statement and then we can try to figure out what they really mean, it's not like ASML can consider the entirety of technology.
 

gelgoog

Lieutenant General
Registered Member
I think he's only talking about lithography technology. But what that means is important. The first EUV machine was installed in 2010. If as we estimate, China will have its first EUV machine in 2025. That makes his statement exactly correct. However it also reveals that China's immersion DUVs are already close to ASMLs. I've always had a suspicion that ASML knows more about Chinese lithography than even we know. His statement makes me believe that SMEE's lithography machine is already in use as we all suspected. We have to remember the source of the statement and then we can try to figure out what they really mean, it's not like ASML can consider the entirety of technology.
He said "chip manufacturing". If we are talking about chip making equipment then China is currently at 65nm node in lithography. The industry leaders came out with production with that node in 2006. 18 years ago. China already has 28nm capable or better equipment for stages other than lithography however.

We know 65nm is the current state of the art in lithography with Chinese chip making equipment because of that Chinese government report asking the industry to use that machine.

You should not expect SMEE's immersion lithography machine to be in mass production yet. At best it is being used in pilot status.
What I think is happening is some players in China can maintain their imported immersion lithography machines, and maybe even upgrade them to higher specs than they originally had. This allows them to buy time until SMEE's immersion lithography machine achieves mass production capable status.
 
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