Regarding the U.S.’s ongoing restrictions on China’s semiconductor development, including the export ban on EUV lithography machines, Fouquet stated that prohibiting the export of these machines to China would cause the country’s semiconductor industry to lag 10 to 15 years. He noted that the ban is indeed effective, according to the report.
China is like 4 years behind the leader in process technology. TSMC N5 came out in 2020.
The rest is guesstimates.
SMIC introduced N+2 in 2021, while TSMC introduced N7+ in 2019. Both have similar density.
Back then you could argue the difference was closer to 2 years behind. Although even back then SMIC had worse yields than TSMC. So maybe 3 years would be more accurate.
It is still to early to tell, but I think a lag of 10 or 15 years is just plain bullshit. Too many smart minds, and too much money in China. They will figure out a way out of the bind the combined West led by the US put them into. One relatively simple answer is just to go vertical and add more layers. This is already the case in NAND (V-NAND), is likely to become the case in DRAM (3D-DRAM), and could also be applied to logic.
For example in logic you could add backside power delivery like Intel is doing with 18A so that the power traces are in a separate layer and don't take up space in the main layers. You could also have multiple layers with transistors. And you could add CVD diamond layers in between the transistor layers to dissipate the heat. The diamond heat dissipation layers would be connected via diamond pillars (TSV).
Alternatively, as a simpler solution, you can take advantage of the fact that a huge chunk of the die area in a modern SoC is cache. So you add all the L2 and L3 cache in a separate layer connected to the logic layers with TSV similar to AMD's 3D V-cache. This way the logic layers can have more transistors.
Then you have the issue of throughput. i.e. that TSMC can "stamp" more transistors per unit of time than say SMIC can. The answer to that can be larger masks and larger wafers.