it is changes in transistor architecture like planar->FinFET->GAA enable die shrinks at the very advanced nodes. It's not like planar die shrinks anymore where just making things smaller is OK, now every shrink needs its own new architecture. Changes in transistor architecture also make the processes much harder, especially fully 3D architectures like GAA.Honestly given that TSMC also struggled with 3 nm on a FinFET architecture I'm beginning to wonder if the shrinking game is still tenable as a driver for performance. Makes me wonder if it wouldn't be a better strategy to stay at a larger node and focus innovation on transistor architecture.
That's why I think advanced packaging and maybe new materials is the next big thing. The big part is that for more advanced nodes, the percentage of the chip that is dark silicon is rising, thermal budgets are being more constrained, etc. These are problems that are IMO easier solved by advanced packaging than even more die shrinking. Stuff like microfluidic IC cooling.