Chinese semiconductor thread II

tokenanalyst

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Keyang Semiconductor Phase II Project Tops Out, Including 3D Advanced Packaging​


On August 20, the topping-out ceremony of the second phase project of Suzhou Keyang Semiconductor Co., Ltd. was held at No. 568 Fangqiao Road, Suxiang Cooperation Zone, Suzhou Industrial Park.

The Keyang Phase II project covers an area of 29 mu and will build a 36,000 square meter high-standard factory building. The project will be laid in March 2024, and is expected to be completed by the end of 2024 and completed in the first quarter of 2025. The construction of the Phase II project will provide a carrier for the company's development and layout for five to ten years.

According to the information, Suzhou Keyang Semiconductor Co., Ltd. is a high-tech enterprise specializing in wafer-level packaging and testing services. Its registered capital is currently RMB 455.05 million. It began planning in 2013 and officially went into mass production in 2014. Its total assets are currently nearly RMB 1.2 billion and its total area is approximately 70 acres. Keyang focuses on the research and development and mass production of advanced packaging and testing technologies. It has a full-size wafer-level packaging product line of 4 inches, 6 inches, 8 inches and 12 inches, and has multiple packaging capabilities such as TSV, WLCSP, and Bumping. CIS sensors and 5G filter chip products can be widely used in automotive electronics, industry, 5G communications, IoT and other fields.

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tokenanalyst

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Guangli Micro (Semitronix) Integrated Circuit Project successfully completed​


August 21, the topping-out ceremony of the Guangli Microelectronics Integrated Circuit EDA Industrialization Base project located in Binjiang District, Hangzhou was held.

The Guangli Micro Integrated Circuit EDA Industrialization Base Project is located in Puyan Unit, Binjiang District, Hangzhou City, facing Rainbow Expressway and protective green space to the north, and Chaoyong Road to the east. It covers an area of 12.3 acres, with a total construction area of about 32,000 square meters and a building height of about 59.95 meters. It is positioned as the company's future headquarters building and R&D production base. The project layout consists of a high-rise factory building and a podium, with 11 floors in the main building and 3 floors in the podium. The design integrates the form of integrated circuits into the building, showing the industry characteristics of technological innovation.

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dingyibvs

Junior Member
Nano master Charles Lieber has arrived in China safely! He used to be a doctoral supervisor at Harvard University. But this year, he was arrested by the US prosecutors and sentenced to 6 months in prison because of his repeated pro-China remarks and helping to guide students considered "dangerous students" by the United States.

However, now that he is out of prison, he flew to China in the name of sightseeing. Unexpectedly, after landing, he decisively announced that he would take up a position at three universities in China, saying that he wanted to train high-end chip talents for China!

View attachment 134521
Where did you hear that from? He's the former chair of Harvard's Chemistry department, arrested in 2020. I see that he got permission to go to Hong Kong last month but haven't seen any other reports.
 

tphuang

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Nano master Charles Lieber has arrived in China safely! He used to be a doctoral supervisor at Harvard University. But this year, he was arrested by the US prosecutors and sentenced to 6 months in prison because of his repeated pro-China remarks and helping to guide students considered "dangerous students" by the United States.

However, now that he is out of prison, he flew to China in the name of sightseeing. Unexpectedly, after landing, he decisively announced that he would take up a position at three universities in China, saying that he wanted to train high-end chip talents for China!

View attachment 134521
hi there,
if you are posting what clearly looks like are translations, can you at least provide the link to the original article?
 

tokenanalyst

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Innovative Synthesis of Ceo2 Nanoparticles for Advanced Chemical Mechanical Polishing.​


Chinese Academy of Sciences (CAS) - Dalian Institute of Chemical Physics


Abstract​

This study aims to synthesize cerium dioxide (CeO2) nanoparticles with enhanced chemical mechanical polishing (CMP) performance through a straightforward chemical precipitation method. Cerium nitrate and ammonia served as the cerium source and precipitating agent, respectively, under a nitrogen atmosphere. By analyzing the mechanism of oxidizing Ce(OH)3 to produce Ce(OH)4/CeO2, the study investigated how adjusting the cerium source concentration and reaction time affected the particle size, crystallinity, and chemical reactivity of CeO2 abrasives. Various characterization techniques, including X-ray diffraction (XRD), scanning electron microscopy (SEM), hydrogen temperature-programmed reduction (H2-TPR), and nitrogen adsorption-desorption isotherms, were utilized to evaluate the synthesized CeO2 particles. The CMP performance of silica film (SiO2 film) wafer was assessed to verify the final ceria performance. The results indicated that a higher cerium source concentration and extended reaction time resulted in increased crystallite size and enhanced CMP performance. The CeO2 particles synthesized in this study exhibited material removal rate (MRR) values (3095.53 Å/min), surpassing those of commercial CeO2 (2553.06 Å/min). This can be attributed to their high crystallinity and enhanced surface oxygen exchange capability. Consequently, this study illustrates the potential of the proposed synthesis method for producing CeO2 abrasives with superior CMP performance, providing valuable insights for optimizing CMP processes in semiconductor manufacturing.

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OptimusLion

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Huawei's HiSilicon Ascend 920 series is expected to achieve small batch production next year, with a scale of about three to four thousand units. These chips are mainly used for internal verification and small-volume verification for key customers, but they do not have large-scale mass production capabilities. The current plan is to gradually replace the existing 910 series with the 920 starting in 2026. In addition, it is also hoped that the 920 can benchmark against NVIDIA's B100 or B200 solutions. However, there is still a large gap in technology, and Ascend still relies heavily on the support of suppliers. .

What Ascend currently needs is HBM3, but there are currently no domestic manufacturers that can match the international level (such as Hynix, etc.). It is estimated that domestic manufacturers may not make a breakthrough until the end of 2025 or the first half of 2026.
 

tphuang

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Huawei's HiSilicon Ascend 920 series is expected to achieve small batch production next year, with a scale of about three to four thousand units. These chips are mainly used for internal verification and small-volume verification for key customers, but they do not have large-scale mass production capabilities. The current plan is to gradually replace the existing 910 series with the 920 starting in 2026. In addition, it is also hoped that the 920 can benchmark against NVIDIA's B100 or B200 solutions. However, there is still a large gap in technology, and Ascend still relies heavily on the support of suppliers. .

What Ascend currently needs is HBM3, but there are currently no domestic manufacturers that can match the international level (such as Hynix, etc.). It is estimated that domestic manufacturers may not make a breakthrough until the end of 2025 or the first half of 2026.
where does this come from? Do you know about this as a fact or just read this somewhere?

Everywhere we read, the update is 910C and not 920.
 
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