Chinese semiconductor thread II

[tokenanalyst]

Dynamic budget analysis of multiple parameters in a lithography system based on the superposition of light intensity fluctuations​

​

Institute of Microelectronics of Chinese Academy of Sciences
University of Chinese Academy of Sciences
Guangdong Greater Bay Area Applied Research Institute of Integrated Circuit and Systems, Guangzhou

Abstract​

Lithography is one of the most critical processes in the manufacturing of micro- and nano-devices. As device critical dimensions continue to shrink, variations in system parameters during the lithography process often result in heavy deviations from the intended targets, making control of these parameters crucial to ensure that lithography results meet process requirements. Gaining a thorough comprehension of how various parameters interact and contribute to lithography errors is significant, and it is equally important to offer precise suggestions for managing these parameters in extreme ultraviolet lithography (EUVL) scanners. This paper analyzes the key physical factors in the light source, illumination system and projection system of EUVL scanners and proposes what we believe to be a new methodology of budget analysis utilizing the superposition of light intensity fluctuations. Then the corresponding characteristics of light intensity fluctuations are analyzed when these parameters have fluctuated through theoretical formula derivation. A mapping model was established between parameter fluctuations and imaging outcomes through the distribution of light intensity. The yield requirements for critical dimension and pattern shift in EUVL are used to determine the exact budget range for each parameter in the proposed methodology. By controlling the parameters according to the budget analysis method proposed in this paper, the deviation between the experimental results from the yield requirements is no more than 0.1% in average. This approach allows for dynamic updating of the control range of relevant parameters based on their distinct characteristics to accommodate the unique fingerprints of various EUVL scanners. Furthermore, based on this adaptive budget range of multiple parameters, it can offer distinct direction for the development of lithography equipment or serve as a clear indication for parameter monitoring.

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[tphuang]

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摩尔线程联合中国移动通信集团青海有限公司、中国联通青海公司、北京德道信科集团、中国能源建设股份有限公司总承包公司、桂林华崛大数据科技有限公司（排名不分先后）分别就三个万卡集群项目进行了战略签约，多方聚力共同构建好用的国产GPU集群。

Moore threads with 3 10k+ card GPU clusters providing 10+ ELOPS computation each that can be used to computer trillion parameter LLMs

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it unveiled MTT S4000 accelerator card, MCCX D800 all in one model training machine, KUAE fusion and 10k+ card KUAE cluster

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Moore threads partners up to provide energy large model for 乐创能源

 

[tokenanalyst]

Photonic equipment company Guangchi Semiconductor (Optorun) Atomic Layer Coating and Etching Equipment Project Completed​

Recently, the atomic layer coating and etching equipment project invested and constructed by Opto-Chi Semiconductor Technology (Shanghai) Co., Ltd. successfully completed the final acceptance.
The atomic layer coating and etching equipment project is located in the 07-17 plot of Baoshan Hi-tech Zone, with a total investment of 548 million yuan, covering an area of 50 mu and a total construction area of 64,400 square meters, of which the first phase has a construction area of about 38,000 square meters, covering standard workshops, R&D office buildings, etc. The project is mainly committed to the manufacturing of new electronic components and equipment, and utilizes the adjustment of the global pan-semiconductor industry chain and the investment and technology integration of related cutting-edge R&D to realize the industrialization and scale of electronic special equipment manufacturing.

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[paiemon]

20% base on what? what calculations? oh yeah unknown sources.
Ok, my "sources" tell me that SMIC has been replacing US made tools with domestic tools and non US tools at a pretty fast pace, that why that huge jump in japanese tools and why NAURA, AMEC, PIOTECH and others has been fast tracking the releases of their high end tools. SMIC and Huawei has been working improving their manufacturing process since 2020, so that article is full of crap.

I think what gets overlooked when looking at yields is what is the expected target/benchmark yield based on process engineering. We know that increasing die size reduces yield as it increases feature complexity, etc. Does increasing die size by 3x compared to a benchmark (in this case a smartphone die) result in a linear decrease in yield (i.e., 3-fold decrease). For argument's sake, lets say it does. If the benchmark yield for the SMIC 7NM process was 75% on a smartphone die, which is your process baseline then 20ish% yield for an Ascend die 3x that size would be right in line with your expectations. Yield values are irrelevant without the proper context and competitive comparison. If the industry standard for a similar process was getting 90% yields for a design of comparable complexity that would be different, but there is no such data point for evaluation. By that token, oil and gas companies should be abysmal failures because they drill thousands of wells prospecting each year and 95%+ of them are duds.

 

[gelgoog]

It is fairly clear that the yields for the Kirin must be significantly high. Or they wouldn't be selling tens of millions of devices with them.
You have to remember that SMIC has much less capacity than TSMC. TSMC had like 140,000 wpm capacity at 7nm in 2021. SMIC had like 70,000 wpm capacity at 14nm. Even after they double the floor space devoted to FinFET production at SMIC their production should still be lower than TSMCs at the same node.

The claims for low yields of the Ascend NPU are probably hyperbole because highly regular chips like that one can have functional units with errors disabled and still work fine. It will just reduce peak performance.

 

[tokenanalyst]

ProPlus NanoSpice™ Passes Samsung Foundry 3/4nm Process Technology Certification​

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ProPlus Semiconductor recently announced that its new generation of large-capacity, high-performance parallel SPICE simulator NanoSpice™ has passed Samsung Foundry's 3/4nm process technology certification, meeting the needs of both parties' common customers for high-end circuit simulation with high precision, large capacity and high performance.
Samsung's 3/4nm process is designed to improve yield, reduce power consumption and improve performance, which requires more accurate circuit simulation and verification tools to achieve more advanced IC design. NanoSpice™ certification is part of Samsung's EDA certification program. The simulator has shown good simulation convergence and accuracy in large-scale post-simulation netlist simulation of analog IP, helping mutual customers design with confidence and ensuring higher accuracy while shortening the design cycle.
As a new generation of high-capacity, high-performance parallel SPICE simulator, NanoSpice™ is designed for the most challenging simulation tasks, such as large-scale post-layout analog circuit simulation that requires high-capacity, high-speed, and high-precision simulation. It is equipped with superior parallel circuit simulation technology and can efficiently handle circuit simulations of more than 50 million components.
Sangyun Kim, Vice President of Samsung Foundry Design Technology Team, said, “NanoSpice™ has achieved a win-win situation through Samsung Foundry’s 3nm/4nm process technology certification. The long-term stable and friendly partnership between Samsung and ProPlus can promote the realization of advanced verification and innovative IC design capabilities to meet the rapidly growing IC market and application needs.”
Dr. Lianfeng Yang, Director and President of ProPlus, said, “Samsung is a long-term customer and ecological partner of ProPlus. We will continue to innovate to meet the simulation challenges brought by future cutting-edge technologies. NanoSpice™ is designed with high performance and high precision. With its full set of simulation capabilities from smaller modules to full chip design, it can meet the most stringent performance and precision design verification requirements, and its performance in a high-precision state is better than other commercial SPICE simulators.”

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[gelgoog]

The Chinese EDA industry is rapidly improving the capabilities of their software. I think without the US sanctions on sales of EDA software it wouldn't have happened.

 

[Hyper]

It is fairly clear that the yields for the Kirin must be significantly high. Or they wouldn't be selling tens of millions of devices with them.
You have to remember that SMIC has much less capacity than TSMC. TSMC had like 140,000 wpm capacity at 7nm in 2021. SMIC had like 70,000 wpm capacity at 14nm. Even after they double the floor space devoted to FinFET production at SMIC their production should still be lower than TSMCs at the same node.

The claims for low yields of the Ascend NPU are probably hyperbole because highly regular chips like that one can have functional units with errors disabled and still work fine. It will just reduce peak performance.

Yields are different for different designs. Ascend is more complex than Kiron so yield will be much lesser because it is much more complex and is a larger die.

 

[gelgoog]

Yields are different for different designs. Ascend is more complex than Kiron so yield will be much lesser because it is much more complex and is a larger die.

Not necessarily. Just like I said, it is highly regular, they can disable cores. On a smaller chip like an SoC any malfunctioning unit is fatal.

 

[latenlazy]

Dynamic budget analysis of multiple parameters in a lithography system based on the superposition of light intensity fluctuations​

​

Institute of Microelectronics of Chinese Academy of Sciences
University of Chinese Academy of Sciences
Guangdong Greater Bay Area Applied Research Institute of Integrated Circuit and Systems, Guangzhou

Abstract​

Lithography is one of the most critical processes in the manufacturing of micro- and nano-devices. As device critical dimensions continue to shrink, variations in system parameters during the lithography process often result in heavy deviations from the intended targets, making control of these parameters crucial to ensure that lithography results meet process requirements. Gaining a thorough comprehension of how various parameters interact and contribute to lithography errors is significant, and it is equally important to offer precise suggestions for managing these parameters in extreme ultraviolet lithography (EUVL) scanners. This paper analyzes the key physical factors in the light source, illumination system and projection system of EUVL scanners and proposes what we believe to be a new methodology of budget analysis utilizing the superposition of light intensity fluctuations. Then the corresponding characteristics of light intensity fluctuations are analyzed when these parameters have fluctuated through theoretical formula derivation. A mapping model was established between parameter fluctuations and imaging outcomes through the distribution of light intensity. The yield requirements for critical dimension and pattern shift in EUVL are used to determine the exact budget range for each parameter in the proposed methodology. By controlling the parameters according to the budget analysis method proposed in this paper, the deviation between the experimental results from the yield requirements is no more than 0.1% in average. This approach allows for dynamic updating of the control range of relevant parameters based on their distinct characteristics to accommodate the unique fingerprints of various EUVL scanners. Furthermore, based on this adaptive budget range of multiple parameters, it can offer distinct direction for the development of lithography equipment or serve as a clear indication for parameter monitoring.

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They’re deep into system optimization territory now I see.