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Chinese semiconductor thread II
- Thread starter vincent
- Start date
TSMC's wafer price.....
View attachment 127848
I don't know where this table was published as there are no sources, but these are MY numbers, I wrote them in the article entitledTSMC's wafer price.....
View attachment 127848
"Taiwan Semiconductor Raising Prices 8.7% In 2024 As Revenue Growth Underperforms Customers"
You can find them in Table 1 and here is the link:High-precision servo control design and optimization for dicing semiconductor wafer.
School of Intelligent Manufacturing and Electronic Engineering, Wenzhou University of Technology
College of Mechanical and Vehicle Engineering, Hunan University,
Zhuzhou CRRC Times Electric Co., Ltd., Zhuzhou 412000, China
Abstract
The dicing of semiconductor wafers is an essential component for fabricating electronic circuits. A servo control approach with high-precision and stability was designed to enhance the positioning accuracy and stability for dicing semiconductor wafers. The principal control and dicing processes were studied. The High Definition closed-loop control algorithm was designed, and the control parameters were optimized. The control performance was enhanced using the PID + Feedforward + NOTCH filter control algorithm. The error detection of linear and rotation axes was designed to compensate servo axis errors by using the laser interferometer and control card. After error compensation, the positioning accuracy and repeatability of the Y-axis were 2.031 μm and 1.889 μm. That of the C-axis were 0.00423°, and 0.00347°. The dicing experiment revealed the maximum chipping width was <10 μm and the dicing channel width was <42 μm. The designed servo control system ensured the high-precision and stable dicing of semiconductor chips.
This is the more relevant graph when it comes to cost, which shows that per transistor cost has been flat or marginally increased. However, despite the cost per transistor being the same, the leading edge nodes are still extremely important because:
- Power Consumption: Smaller node sizes required less power. As such power consumption improvements are huge. By my calculations, the 2 nm node is projected to have a power consumption that is ~90% less than 28 nm. (Maybe more knowledgeable people can correct me if I am off by much). This is important in many downstream applications:
- Mobile SoCs: With 90% less consumption, your phone can run more intense applications, or run them for longer. Longer battery life, one of the core competencies in a phone.
- GPUs: These days modern GPUs are energy guzzlers, with Nvidia's latest consuming 1000W+. Let's calculate the energy savings that this GPU gets in a year. If running constantly for a year, it consumes ~ 8.8 MWh of energy, similar performance on a larger node might take ~88 MWh of energy, so energy savings of ~ 80 MWh. With energy prices of let's say 30 cents per kWh, this is a cost savings of ~24000 USD in electricity prices alone.
- Some applications are simply impossible or exceedingly tough with high power consumption. So if say, needed to provide 10kW of power vs 1kW of power, the peripherals, and engineering complexity of managing this increases more than linearly.
- Compute Density: Compute Density counts, it's not just about aggregate computing power. The reason being, again based on applications:
- Smaller Footprint: Important for applications like Mobile Phone SoCs
- Actual exploitable compute: Anyone who has handled multiple GPUs will tell you that one large GPU with say x FLOPS is MUCH BETTER than 8 smaller GPUs with x/8 FLOPS. This is because when there's a single GPU, the compute is just more efficient, the data latencies (very important in AI applications) are small, the interconnect is not a bottleneck, there is less number of data shuffling, node management, and a thousand different complications of distributed systems involved. You can simply not get same effective performance from these smaller GPUs in parallel as compared to a single large GPU.
- Since I am not an expert there might be more reasons for favoring smaller nodes, but these two above are abundantly clear.
Using genetic algorithms for maglev stage optimization.
According to the increasing throughput and precision requirements of the wafer stage, this paper proposes a new 2-D magnet array to improve the acceleration and force precision of the planar motor. Firstly, an analytical model of the magnet array with chamfered magnets is established based on the harmonic model, in which the influences of the installation height and the magnetization are included. Then, a modified discrete element model of the runway-type coil is proposed to achieve accurate and efficient force calculation because over half of the force ripple is generated by the coil end, which is neglected in the simplified model. Finally, the influence of chamfered magnet array on the field and force is analyzed. The genetic algorithm is used to optimize the planar motor, which results in a 64% reduction in vertical force tipple and a 1.24 times increase in horizontal acceleration.
Introduction
The wafer stage based on the magnetic levitation planar motor (MLPM) is one of the three core components of EUV lithography because of its simple structure and vacuum compatibility. With the increasing demands for throughput and linewidth, the next-generation EUV needs to increase the precision and acceleration of the wafer stage more than twice [1], [2], [3]. It poses a higher challenge to the design of MLPM.
Solution
Firstly, the topology and modeling of the novel chamfered magnet array (NCMA) with different heights and staggered installations are established. The magnet with chamfers can be regarded as a combination of a square magnet and a triangular magnet. Secondly, by analyzing the actual and simplified models of the runway-shaped coils, it is found that over half of the harmonic forces are distributed at the coil end, which is usually ignored to improve the computation speed. Therefore, this article proposes a modified discrete element method (MDEM) and verifies its correctness through the finite element method. Next, the impacts of the structural parameters on magnetic flux density and force are analyzed and provide references for the optimal design. Finally, the optimal topology is obtained using the genetic algorithm (GA) and performs better.
Optimization of acceleration and force ripple of planar motor based a chamfered magnet array considering coil end effect.
According to the increasing throughput and precision requirements of the wafer stage, this paper proposes a new 2-D magnet array to improve the acceleration and force precision of the planar motor. Firstly, an analytical model of the magnet array with chamfered magnets is established based on the harmonic model, in which the influences of the installation height and the magnetization are included. Then, a modified discrete element model of the runway-type coil is proposed to achieve accurate and efficient force calculation because over half of the force ripple is generated by the coil end, which is neglected in the simplified model. Finally, the influence of chamfered magnet array on the field and force is analyzed. The genetic algorithm is used to optimize the planar motor, which results in a 64% reduction in vertical force tipple and a 1.24 times increase in horizontal acceleration.
Introduction
The wafer stage based on the magnetic levitation planar motor (MLPM) is one of the three core components of EUV lithography because of its simple structure and vacuum compatibility. With the increasing demands for throughput and linewidth, the next-generation EUV needs to increase the precision and acceleration of the wafer stage more than twice [1], [2], [3]. It poses a higher challenge to the design of MLPM.
Solution
Firstly, the topology and modeling of the novel chamfered magnet array (NCMA) with different heights and staggered installations are established. The magnet with chamfers can be regarded as a combination of a square magnet and a triangular magnet. Secondly, by analyzing the actual and simplified models of the runway-shaped coils, it is found that over half of the harmonic forces are distributed at the coil end, which is usually ignored to improve the computation speed. Therefore, this article proposes a modified discrete element method (MDEM) and verifies its correctness through the finite element method. Next, the impacts of the structural parameters on magnetic flux density and force are analyzed and provide references for the optimal design. Finally, the optimal topology is obtained using the genetic algorithm (GA) and performs better.
Of course smaller transistor good like water is wet, the problem is the price increase per node, the rate of increase is from my point view is too fast.This is the more relevant graph when it comes to cost, which shows that per transistor cost has been flat or marginally increased. However, despite the cost per transistor being the same, the leading edge nodes are still extremely important because:
- Power Consumption: Smaller node sizes required less power. As such power consumption improvements are huge. By my calculations, the 2 nm node is projected to have a power consumption that is ~90%less than 28 nm. (Maybe more knowledgeable people can correct me if I am off by much). This is important in many downstream applications:
- Mobile SoCs: With 90% less consumption, your phone can run more intense applications, or run them for longer. Longer battery life, one of the core competencies in a phone.
- GPUs: These days modern GPUs are energy guzzlers, with Nvidia's latest consuming 1000W+. Let's calculate the energy savings that this GPU gets in a year. If running constantly for a year, it consumes ~ 8.8 MWh of energy, similar performance on a larger node might take ~88 MWh of energy, so energy savings of ~ 80 MWh. With energy prices of let's say 30 cents per kWh, this is a cost savings of ~24000 USD in electricity prices alone.
- Some applications are simply impossible or exceedingly tough with high power consumption. So if say, needed to provide 10kW of power vs 1kW of power, the peripherals, and engineering complexity of managing this increases more than linearly.
- Compute Density: Compute Density counts, it's not just about aggregate computing power. The reason being, again based on applications:
- Smaller Footprint: Important for applications like Mobile Phone SoCs
- Actual exploitable compute: Anyone who has handled multiple GPUs will tell you that one large GPU with say x FLOPS is MUCH BETTER than 8 smaller GPUs with x/8 FLOPS. This is because when there's a single GPU, the compute is just more efficient, the data latencies (very important in AI applications) are small, the interconnect is not a bottleneck, there is less number of data shuffling, node management, and a thousand different complications of distributed systems involved. You can simply not get same effective performance from these smaller GPUs in parallel as compared to a single large GPU.
- Since I am not an expert there might be more reasons for favoring smaller nodes, but these two above are abundantly clear.
Wow prices are growing up pretty fast, looks like EUV is not the savior technology that everyone thought was gonna be.
View attachment 127851
For the price rate increase that we are seeing the performance from 3nm to 2nm should be enormous, like from 90nm to 65nm was a big increase in performance but the price per wafer increase was just 300 hundred dollars, that means better performance devices for cheaper prices, huge economic boom in electronics.
I think that at manufacturing process costs increase fabs will not want to use expensive tooling like ASML High NA EUV machines to make el cheapo GPUs with low margins for you average gamers, these expensive and deliciated EUV machines will be relegated high margin expensive products like AI processors, that will be a problem as this machines become obligatory to make advance nodes.
Different from the DUV dry and immersion era when ASML and Nikon machines where basically unbreakable workhorses patterning chips for everyone from the cheap smartphone of an Africa farmer to the low budget gaming machine of a McDonald college worker in Illinois. Like I said before, the dimensional scaling problem could be solved using geometric scaling 3D-transistors and/or advance packaging. The cost problems that is another issue, that could be solved with projects like China EUV-SSMB that will deliver massive amount of very clean EUV power to multiple workstations that if combined with a fasters reticle and wafers stages and alignment/overlay systems could increase the WPH output massively decreasing prices allowing again cheaper below 5nm devices to the masses even if dimensional scaling reached the wall.
According to TSMC, its 3nm process increases speed by at the same power or reduces power consumption by 25%-30% at the same speed compared to its 5nm process. In benchmarks, performance per watt for Apple M3 CPU (TSMC 3nm) is only better than that of the Apple M2 CPU (TSMC 5nm).
It is getting increasingly difficult to shrink the transistors because of electron leakage and quantum tunneling effects. They went vertical but that does not solve everything.For the price rate increase that we are seeing the performance from 3nm to 2nm should be enormous, like from 90nm to 65nm was a big increase in performance but the price per wafer increase was just 300 hundred dollars, that means better performance devices for cheaper prices, huge economic boom in electronics.
High NA EUV is a boondoggle. Have you looked at the size of the machines? Unless someone comes up with a more energy efficient, high power, light source it will continue being so. They went from a lithography machine the size of a car with Low NA EUV, to a lithography machine the size of a truck with High NA EUV. And that is by cutting the size of the mask in like half. Had they scaled up the size of the mask, like they should have to increase production rate to make it economic in production, the light source would need to be even higher power to have the proper wafer exposure. An even bigger machine. You need a huge high power CO2 laser light for LPP and then you get a pittance of that converted into actual EUV light with the tin drop chamber.I think that at manufacturing process costs increase fabs will not want to use expensive tooling like ASML High NA EUV machines to make el cheapo GPUs with low margins for you average gamers, these expensive and deliciated EUV machines will be relegated high margin expensive products like AI processors, that will be a problem as this machines become obligatory to make advance nodes.
EUV-SSMB keeps looking better and can't show up fast enough in my opinion. I think the regular Low NA EUV is basically the limit for conventional lithography machines.Different from the DUV dry and immersion era when ASML and Nikon machines where basically unbreakable workhorses patterning chips for everyone from the cheap smartphone of an Africa farmer to the low budget gaming machine of a McDonald college worker in Illinois. Like I said before, the dimensional scaling problem could be solved using geometric scaling 3D-transistors and/or advance packaging. The cost problems that is another issue, that could be solved with projects like China EUV-SSMB that will deliver massive amount of very clean EUV power to multiple workstations that if combined with a fasters reticle and wafers stages and alignment/overlay systems could increase the WPH output massively decreasing prices allowing again cheaper below 5nm devices to the masses even if dimensional scaling reached the wall.