Chinese semiconductor thread II

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tokenanalyst

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Gallium Semiconductor launches 2-inch wafer-level gallium oxide single crystal substrate.​

Hangzhou Gallium Semiconductor Co., Ltd. (hereinafter referred to as "Gallium Semiconductor") announced the official launch of a 2-inch wafer-level (010) gallium oxide single crystal substrate, setting another new milestone in the R&D and production of (010) substrates.
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According to reports, gallium oxide (β-Ga2O3) has the advantages of large bandgap width, high breakdown field strength, and large Baliga figure of merit, allowing power devices based on gallium oxide to have larger operating currents, voltages, and smaller On-resistance, device size and higher conversion efficiency are mainly used to prepare power devices, radio frequency devices and detection devices. They have broad applications in rail transit, smart grids, new energy vehicles, photovoltaic power generation, 5G mobile communications, national defense and military industries and other fields.

It is worth mentioning that previously, Gallium Semiconductor, in conjunction with the Advanced Semiconductor Research Institute of Zhejiang University Hangzhou International Science and Technology Innovation Center and the National Key Laboratory of Silicon and Advanced Semiconductor Materials, successfully prepared high-quality 6 inch unintentionally doped and conductive gallium oxide (β-Ga2O3) single crystal, and processed to obtain a 6-inch gallium oxide substrate. Gallium Semiconductor has also become the first industrialized company in China to master the preparation technology of 6-inch gallium oxide single crystal substrate.

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tphuang

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More from Silan full year report
They had 6000 wpm of SiC MOS capacity at end of 2023 and looking expand to 12k 6-inch wpm. That's pretty huge. Mostly to be used in EV electric drive module

It has 140-150k wpm of 4-inch LED production. That's pretty large too. There was demand drop last year for this

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Nexchip apparently is now capable of mass producing 50 Megapixel CIS since it has mastered 90nm and 55nm CIS production. So another other for probably lower end 50 megapixel to be fabbed. I think SMIC is probably at 40nm at this point
 
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latenlazy

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A Unified Machine Learning Through Focus Resist 3-D Structure Model​


Shanghai Integrated Circuits R&D Center, Shanghai, China

Abstract:
To ensure post OPC data quality, examination based on estimated resist contours at resist bottom alone is insufficient, reliable prediction of lithography performance within process window must rely on complete information of on-wafer resist 3D structures. In this regard, resist 3D structure model, in particular, the through focus resist 3D structure model, with full chip capability will be the ultimate model in demand. To develop machine learning resist 3D structure models,we have proposed the physics-based information encoding scheme, together with carefully chosen deep convolution neural network and model training strategies. Our proposed through focus resist 3D structure model is based on conditional U-net structure with first five eigen images as model’s main inputs and the focus setting as the conditional input. The average normalized cross correlation (NCC) or mean structure similarity index between ground truth and model predicted resist 3D structures can reach 0.92. With single GPU (Tesla M60), it takes 6.1ms for the model to produce resist 3D structure covering area of 1.8umx1.8 μm . The model is fast enough and can be engineered for full chip implementation. The model can extend the capability of detecting lithography process window aware resist loss related hotspots.


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Zhaoming Semiconductor's annual output of 100 million photonic integrated chips project starts​


According to the "Pujiang Release" public account, on April 8, Pujiang County held the groundbreaking ceremony of Zhaoming Semiconductor's annual output of 100 million photonic integrated chips project and the on-site meeting of Pujiang County's first critical action for project construction in 2024. It is reported that the total investment of Zhaoming Semiconductor's annual output of 100 million photonic integrated chips is about 2.65 billion yuan, which will be constructed in two phases. Among them, the first-phase project will invest 1.18 billion yuan to build a photonic integrated chip project with an annual output of 100 million units. It is planned to complete the factory construction and put into operation before the end of June 2025; the second-phase project will invest 1.47 billion yuan to build a photonic integrated chip project with an annual output of 200 million units. Chip process lines, semiconductor materials, packaging and other production projects. After the project reaches full production, it is expected to achieve annual sales revenue of 2 billion yuan and tax revenue of approximately 120 million yuan.

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The foundation laying and groundbreaking ceremony of the Shenyang Semiconductor Precision Slicing Equipment R&D and Industrial Base Construction Project was successfully completed!​


The Heyan semiconductor dicing machine R&D and industrial base project plans to invest a total of 360 million yuan and cover an area of 87 acres. After the project is completed, it will not only build a series of modern precision R&D laboratories, process laboratories, digital intelligent workshops, and intelligent warehouses, etc. R&D and production base, and can build a production, research and marketing management platform that integrates digital intelligence, informatization and intelligence. Witnessed by leading guests and employee representatives, the opening ceremony of Heyan Technology's semiconductor precision dicing equipment research and development and industrial base construction project was a complete success.​

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Precision Wafer Dicing Machines:

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AF-1

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olalavn said:
TSMC's wafer price.....
View attachment 127848
Click to expand...
Those prices are not a real parameter for generations gap in price. 12-inch 2nm wafer contains much much more transistors than 90nm ones, so this huge gap in price per wafer is pretty much lower when apply to single chip/transistor...
On same wafer size, you get much more and superior chips than before, so price must go up :)
 
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tokenanalyst

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AF-1 said:
Those prices are not a real parameter for generations gap in price. 12-inch 2nm wafer contains much much more transistors than 90nm ones, so this huge gap in price per wafer is pretty much lower when apply to single chip/transistor...
On same wafer size, you get much more and superior chips than before, so price must go up :)
Click to expand...
The problem is not the prices per se but the rate of price increasing, you are not getting the far superior performance from one generation to another generation per price increasing. That means that the cost per transistor is slowing down in dimensional scaling, so the only option for more performance could geometrical scaling but that comes with its own set of challenges.
 
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zbb

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AF-1 said:
Those prices are not a real parameter for generations gap in price. 12-inch 2nm wafer contains much much more transistors than 90nm ones, so this huge gap in price per wafer is pretty much lower when apply to single chip/transistor...
On same wafer size, you get much more and superior chips than before, so price must go up :)
Click to expand...

tokenanalyst said:
The problem is not the prices per se but the rate of price increasing, you are not getting the far superior performance from one generation to another generation per price increasing. That means that the cost per transistor is slowing down in dimensional scaling, so the only option for more performance could geometrical scaling but that comes with its own set of challenges.
Click to expand...

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