Breaking the Moore's Law Era: Silicon Core Technology Reconstructs the 2.5D/3D ICEDA Process with STC
On May 27th at the Shanghai Zhangjiang Science Hall, the 10th AI Chip Conference hosted a landmark session focused on breaking free from the constraints of Moore's Law through advancements in silicon core technology. The event, part of a broader effort to foster ecosystem collaboration for China's semiconductor industry, featured a keynote speech by Dr. Zhao Yi, Founder and CEO of Zhuhai Silicon Core Technology (STCO). Speaking at this "Advanced Packaging and Testing Technology Innovation Summit," Dr. Zhao outlined how the global chip development logic is fundamentally shifting from single-chip performance iteration to system-level architectural optimization driven by artificial intelligence.
Dr. Zhao argued that traditional lithography limits are reaching a physical ceiling, making further reliance on process miniaturization insufficient for meeting future demands. Instead, the industry is urgently transitioning toward 2.5D and 3D integrated circuit (IC) stacking architectures. This approach, which involves vertically stacking bare dies rather than expanding horizontally, restructures interconnect mechanisms and design boundaries to unlock significant performance gains. Citing precedents set by giants like Broadcom and AMD in their pioneering of the 3.5D concept, Dr. Zhao predicts that by mid-2026, both domestic and global markets will witness a wave of large-scale innovation based on these stacked architectures, marking a comprehensive restructuring of design methods and industry paradigms beyond mere manufacturing upgrades.
To support this shift, the industry is moving from the traditional "Devices-Technology Co-Optimization" (DTCO) model to a new paradigm called "System-Technology Co-Optimization" (STCO). In the old DTCO model, design focused on adapting a single chip's device performance to the manufacturing process. However, in heterogeneous stacking scenarios involving multiple nodes and chip types, optimal performance requires top-level system architecture that dictates the design of individual chips. Dr. Zhao emphasized that this represents a qualitative leap where packaging shifts from passively adapting to design to actively leading it, requiring early-stage modeling of I/O planning, power distribution, thermal stress, and warpage risks across diverse chip types including logic, memory, RF, and silicon photonics.
The implementation of STCO necessitates a complete overhaul of the Electronic Design Automation (EDA) toolchain, which currently serves as a critical bottleneck. Traditional single-chip EDA engines struggle with the vertical interconnects and cross-layer complexities of 3D stacking. Silicon Core Technology has responded by developing dedicated design engines capable of optimizing high-speed differential signals and heterogeneous interfaces. Furthermore, leveraging Huawei's "Tao's Law," STCO promotes simultaneous design and simulation; their tools reportedly reduce a project requiring two months of serial iteration to just ten days of collaborative convergence while prioritizing reliability through early-stage analysis of stress distribution and defect probability rather than post-production correction.
At the testing verification stage, Dr. Zhao highlighted that the high integration cost of stacked chips means any single-point failure can scrap an entire wafer, rendering traditional standards obsolete. He noted STCO's involvement in developing the IEEE 1838 standard, which addresses these challenges through on-chip redundancy and self-healing mechanisms, alongside dedicated bidirectional interconnect rule bases for accurate foundry adaptation. Addressing these needs, Silicon Core Technology has independently launched the 3Sheng Integration Platform, reportedly the first EDA platform in China to cover the entire 2.5D/3D stacked chip design process.
The 3Sheng Integration Platform offers a closed-loop solution spanning system architecture, physical implementation, co-simulation, fault tolerance testing, and multi-chiplet verification. It is designed to support diverse applications ranging from AI and GPU/CPU processing to silicon photonics, enabling high-performance integration for heterogeneous computing scenarios. From a macro-industry perspective, the rise of this STCO paradigm presents a strategic opportunity for domestic EDA companies to leapfrog by competing not just on single-chip specs but on holistic system collaboration capabilities. Dr. Zhao concluded by urging deep industry-wide cooperation across process, equipment, materials, and design sectors to build a robust domestic advanced packaging ecosystem capable of overcoming cost barriers and external technological blockades.
