Just to help elaborate what I mean by a “tick-tick-tock” cadence I made the above illustration based on the chart Huawei presented two days ago.
As a point of comparison, TSMC 3 nm transistor density is listed as 224 MTr/mm2 and apparently TSMC 2 nm will only be a 15-20% improvement in density, ~268 MTr/mm2, which suggests TSMC will have to relax transistor spacing either for yield or transistor performance purposes, showing diminishing returns in transistor density gains past the 3 nm node. TSMC's roadmap after 2 nm will be 1.6 nm in 2027, 1.4 nm 2028, and then 1.2-1.3 nm in 2029, assuming no hitches and delays, with each supposed to yield ~7-10% improvement in transistor density. In other words TSMC is shifting from 50% node shrinks every 2-3 years to much more modest ~10-15% shrinks every year. Only by 2029, 3-4 years after 2 nm entered mass production, will TSMC get to another 50% node shrink, with a transistor density improvement of about 30% assuming the optimistic case of 10% density gain every iteration, or ~348 MTr/mm2. If they can sustain that annual 10% density gain going forth they will reach ~420 MTr/mm2 by 2031.
Meanwhile, Huawei is forecasting in their chart ~6% improvements in transistor density every year until 2030, before you get a massive jump into 400+ MTr/mm2 territory. While entirely conjectural on my part it's imo plausible that Huawei could be planning to introduce annual node shrink cadences with very conservative transistor spacing that focus less on density and more on per cycle time energy efficiency, while reaping the rest of their performance gains through per watt clock speed improvements of ~9-10% as they continuously optimize 3D layouts for a 2 layer "fold", and then reach their massive transistor density leap in 2031 by adding another "fold" layer at a more conservatively designed 2-3 nm node.
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