Chinese semiconductor thread II

tokenanalyst

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A Core structural design strategy for molecular resists based on inhibiting acid diffusion and reducing deprotection stochasticity​

Abstract​

As lithographic resolution improves, stochastic effects during the lithography process have become increasingly significant in influencing pattern quality. Compared to polymeric resists, Single-molecule resins (SMRs), also known as molecular glasses, exhibit potential for mitigating development stochasticity due to their smaller molecular size and monodisperse nature. This study aims to investigate the relationship between the core structure of SMRs and their lithographic stochastic effects. To this end, we designed a series of bisphenol-A-like SMRs with core structures of adamantane-diyl, isopropylidene and isopropylidene, namely AD-Boc, BPA-Boc, and PH-Boc. Performance evaluations revealed the ranking in terms of LER and contrast: AD-Boc > BPA-Boc > PH-Boc. Fourier-transform infrared spectroscopy (FTIR) and X-ray reflectivity (XRR) analyses demonstrated that AD-Boc exhibits the strongest capability to suppress acid diffusion. Furthermore, calculations of the critical deprotection ratio combined with surface energy measurements confirm that AD-Boc induces the least stochasticity during development. These two effects together account for the observed differences in final lithographic performance. This work elucidates how the core structure of SMRs modulates lithographic performance by controlling acid diffusion and development stochasticity, providing valuable insights for the design of next-generation photoresists.​

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tokenanalyst

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GAA Device Process PDK and Standard Cell Library​

Research content:
This research investigates the physical effects of advanced devices such as nanoscale FinFETs and GAAs, including layout-dependent effects (LDE), parasitic effects, and size fluctuations. It also develops collaborative optimization technologies for design and manufacturing, such as process-integrated device models, PDKs, standard cell libraries, and integrated circuit design reference flows.​

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Clark Gap

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its from Zheng Jun, the CTO of the Huawei Financial System Department.

Zheng Jun said:​

“Chips are developing based on Tao (τ) Law have been applied to the Huawei Mate 90 model, achieving a top-tier process level close to 3nm.”

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Mate90 is going to release either in September or October this year.

If you take a close look at the performance/efficiency growth chart for the 2026 and 2027 products (CPU/GPU/NPU) from the next day's launch event, you should notice that the 9050 can only reach the level of the Snapdragon 8 Gen 3, while the 9060 has a chance to get close to the Snapdragon 8 Elite level — and then further improve the user experience through software optimization.

Kirin 9030 VS 9050 VS 9060
View attachment 175583
 

PopularScience

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AMEC mentioned that in advanced memory device manufacturing processes, over 300 of its independently developed etching machines for ultra-high aspect ratio etching processes have achieved stable and reliable large-scale mass production. Regarding CCP products, those used in critical etching processes continue to experience rapid growth. The next-generation 90:1 ultra-high aspect ratio cryogenic etching equipment has been delivered to clients for verification, and the company now comprehensively covers all ultra-high aspect ratio requirements in memory etching applications. In terms of ICP, the second-generation ICP etching equipment, Primo Angnova™, suitable for manufacturing next-generation logic and memory chips, has achieved a high aspect ratio etching result of 140:1 and excellent topography control in 3D DRAM applications, and has been delivered to leading domestic memory clients for certification.
 

PopularScience

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If you take a close look at the performance/efficiency growth chart for the 2026 and 2027 products (CPU/GPU/NPU) from the next day's launch event, you should notice that the 9050 can only reach the level of the Snapdragon 8 Gen 3, while the 9060 has a chance to get close to the Snapdragon 8 Elite level — and then further improve the user experience through software optimization.
the biggest hurdle is EDA software that support 3D folding.
 

Naladona

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Huawei HiSilicon's presentation at ISCAS 2026 on May 26.
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Video of the presentation
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Session:
Topic 1: Practices of SoC Design with Novel Architectures
Huang Yong, Huawei Fellow, Chief Architect of Kirin and Balong

Topic 2: Computing Chip Design: Engineering Choices and Trade-offs
Xia Jing, Huawei Fellow, Chief Architect of Kunpeng and Ascend Processor

Panel Discussion: Time Scaling, The New Scaling Law
Liao Heng, Huawei Fellow, Chief Scientist of Semiconductor
Handel H. Jones, International Business Strategies, Inc. (IBS), Founder and CEO
Chen Yiran, Duke University, John Cocke Distinguished Professor of ECE, Director, NSF AI Institute Athena
Giovanni De Micheli, EPFL, Director, Integrated Systems Laboratory, Scientific Director, EcoCloud
Wu Huaqiang, Tsinghua University Professor
Xie Yuan, HKUST Professor


Xia Jing’s Zhihu Pin posted on May 28
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snake070

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Interviewee: Xu Zhijun, Rotating Chairman of Huawei

Summary: According to Huawei's data, the CPU clock speed has been boosted from 2.6GHz to 3.1GHz, with NPU performance increasing by 1.4 times and GPU performance seeing a 30%–40% uplift, all while significantly slashing power consumption.
What's even more crucial is that Logic Folding is process-agnostic. It works just as well on 28nm and 7nm nodes, and will remain applicable for future 3nm processes. It even allows for different process nodes to be used across stacked dies. "However, it doesn't reject geometric scaling," Xu repeatedly emphasized. "Domestic advanced processes must and will continue to move forward. Each step forward in process technology will yield better results for the Tau (τ) theory, and conversely, the Tau theory can leverage advancements in process technology to deliver even greater outcomes."
But the greatest cost has been time itself. Logic Folding requires rerouting and layout within a "discontinuous space," a task impossible for traditional EDA tools. It took HiSilicon years of developing proprietary in-house tools to get to this point. Tens of thousands of engineers spent six years navigating blind alleys to turn this concept into a reality, resulting in 381 mass-produced chips.
The path is indeed widening. Guided by the Tau theory, Huawei is achieving Tau scaling in large-scale AI computing clusters through three synergistic layers: the Unified Bus interconnect architecture, the near-package optical engine Hi-ONE, and the topological reorganization of the packaging itself via 3D Folding.
The Super Node architecture interconnects multiple chips at high speeds to form a logical "super chip." This extends the logic of time scaling from a single chip to the entire computing system. As a result, even with a lag in manufacturing process technology, Huawei's AI computing clusters are positioned to outperform NVIDIA.
 

tphuang

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China's memory chip export was huge in 2026Q1. Great for the industry all along, but I'd imagine it really helped CXMT and YMTC also.

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Jingce says it received 516m RMB of orders recently for various semi testing equipment for usage in advanced memory products.
 

Michael90

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Tesla will be banned in China in retaliation.
Nahhhhh…China is not the US. So they won’t adopt such measures since they know competition is good for the country. Tesla and Chinese evs have been banned in the said since years now. Ask yourself why has China not retaliated on Tesla ?
 
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