Chinese semiconductor thread II

[tphuang]

Huawei Unveils AI Accelerator Ascend 950 with 3x H20 Performance: Achieving NVIDIA H200 Levels Possible with 3nm and HBM3 Application

The Ascend 950, combining a 3nm process with HBM3, has become powerful enough to be called the **"Chinese version of the H200"**.

Carbon Nanotube (CNT) Semiconductor: This is the most groundbreaking aspect. It has already been verified at the laboratory level and is currently being optimized for SMIC's production lines. If successful, it could become a "game changer" capable of overcoming the physical limitations of existing silicon chips and demonstrating energy efficiency exceeding that of the H200.

it is not H200. They are not comparable. They are in fact built on different philosophies. Why would anyone compare Ascend-950 with a vastly downgraded chip like H20? I understand that you probably copy and pasted something you saw someone else post, but if they write stuff like this, maybe you should not repost it.

Do you have a source for this? I can't find this online and I'm skeptical that Ascend 950 is on a 3nm process considering that it seems SMIC only got to 6nm fairly recently and I'm kinda skeptical Huawei would be able to trick TSMC into fabbing a lot of chips for them again.

Ascend-950 is probably using N+2 process

He/she is spreading semi-false information, the reality is 1.56PFLOPS PF4, ~40% H100, while the power is 600 watt, which is quite disappointing considering the power of H100 SXM is around 700 watt; besides, the bandwith is dissppointing as well with 1.4TB/S, ~47% H100 SXM. So we may infer from it that this chip is made with HBM2e or equivalent VRAM chip and its power efficiency is roughly the same as Ascend 910B, which is quite strange because it even cannot match the level of Ascend 910C. I wonder if it is because they are shifting away from NPU so that the version 1 has low power efficiency.

Please, Log in or Register to view URLs content!

Please, Log in or Register to view URLs content!

Please, Log in or Register to view URLs content!

again for Nvidia. Sparsity vs Dense, make sure you know what you are comparing. Nvidia likes to advertise sparsity figures.

If you cannot understand why Ascend-950 has lower compute than 910C, then you are probably not qualified to comment. Also we don't know the power consumption of Ascend-950. We know that Ascend950PR is rated as 1 PFLOPS FP8/MXPF8 & using HIBL 1.0 with 128 GB of memory. We know the chip to chip interconnect is 2 TB/s

Ascend 950 is not meant to compete with Nvidia cards on a card level performance. Instead they are focusing on cluster level performance (ie, bigger clusters than Nvidia). On a single card level it actually has less compute than Huawei's previous product Ascend 910C.

Numbers for Ascend 950 and several subsequent products are in Huawei's public roadmap for next several years. Ascend 950 is most likely 7nm chip with HBM2E for the inference version and HBM3 for the training version. From the roadmap it's very clear they are not trying to match Nvidia cards one-on-one any time soon. Their focus is bigger clusters and better networking.

Do you understand why Ascend-950 has lower per chip compute than 910C? This is critical to understand the design decisions behind 950 series.

 

[tokenanalyst]

Heptagon – Next Generation of Optical Innovation​

Heptagon, a brand under Juguang Technology, is committed to becoming your trusted photonics manufacturing partner, empowering continuous innovation in the global photonics industry by leveraging leading wafer-level micro-nano optical technology.

Leveraging core technologies including wafer-level optical precision imprinting, wafer-level stacking processes , and wafer-level module integration , we can design and mass-produce a variety of high-performance micro/nano optical devices and modules compatible with surface mount technologies. Our products cover planar/hybrid optical elements, diffractive optical elements (DOE), microlens arrays (MLA), projection and imaging optical components, miniature camera lenses, miniature projection lenses, as well as optical sensing and illumination modules. Our solutions are widely used in diverse fields such as consumer electronics, smart mobility, healthcare, smart homes, and optical communications, continuously creating "smart" value for various industries.


In addition, Heptagon provides customized one-stop manufacturing services for global photonics industry customers, covering the entire process from early concept to large-scale mass production, helping to transform customers' innovative ideas into scalable and manufacturable optical solutions and improve the end-user experience.

Please, Log in or Register to view URLs content!

 

[tokenanalyst]

MM-WAE: Multimodal Wasserstein Autoencoders for Semi-Supervised Wafer Map Defect Recognition​

Abstract​

Wafer map defect pattern recognition is a key task for ensuring yield in integrated circuit manufacturing. However, in real production lines it commonly suffers from scarce labeled data, long-tailed class distributions, and limited feature representations, which cause existing deep learning models to degrade in performance, particularly for minority defect classes and complex defect morphologies. To address these challenges, we propose a semi-supervised classification method for wafer maps based on a multimodal Wasserstein autoencoder (MM-WAE). The framework constructs three parallel feature branches in the spatial, frequency, and texture domains, using a multi-head attention mechanism and gating mechanism for adaptive multimodal fusion. This allows defect patterns to be comprehensively characterized by macroscopic geometric distributions, spectral periodic structures, and microscopic texture details. The Wasserstein autoencoder is introduced, with the latent space distribution regularized by a maximum mean discrepancy (MMD) loss using an inverse multiquadratic kernel. Additionally, an inverse class-frequency weighted cross-entropy loss and a modality consistency loss between the encoder and classifier jointly optimize the reconstruction and classification paths while leveraging large amounts of unlabeled wafer maps for semi-supervised learning. Experimental results show that MM-WAE mitigates performance limitations caused by insufficient labels and class imbalance, significantly improving the accuracy and robustness of wafer defect classification, with promising potential for industrial application and further development.​

Please, Log in or Register to view URLs content!

 

[tokenanalyst]

ACM Shanghai launched stress free CMP.

Stress Free Polishing Systems—Ultra SFP​

ACM Ultra SFP: A Unified, Stress-Free Polishing and Planarization System​

The ACM Ultra SFP is an advanced semiconductor tool designed to streamline Through-Silicon Via (TSV) and Fan-Out Wafer-Level Packaging (FOWLP) processes. By combining proven stress-free polishing (SFP) technology with external CMP and wet-etch capabilities into a single integrated system, it addresses common yield issues such as copper overburden and wafer warpage.

• Integrated Workflow: Unifies SFP polishing, chemical mechanical planarization (CMP), and wet etching in one platform, eliminating the need for multiple separate machines.
• Proprietary Mechanism: Utilizes a unique electrochemical process that delivers electrolytes and power simultaneously to rotating wafers, electrically removing metal ions rather than relying solely on abrasion.
• Advanced Process Flowesigned for multi-step removal sequences:
  1. SFP removes bulk copper overburden (down to ~0.2µm).
  2. CMP planarizes the surface down to the titanium barrier layer.
  3. Wet-etch strips titanium, exposing the final oxide layer.

Environmental & Economic Benefits:

• Sustainability: Features a built-in recycling system that reuses electrolytes and wet-etchants in real-time, drastically reducing chemical consumption and waste compared to conventional toxic CMP methods.
• Stress Elimination: ACM's unique three-step approach effectively removes process-induced stress from wafers during polishing.
• Cost Efficiency: Lowers the total cost of ownership by minimizing consumable usage, enhancing metal recovery for reuse, and reducing disposal costs.

Performance Specifications:

• Removal Rate: 0.5µm/minute
• Uniformity: Within-wafer <3%; Wafer-to-wafer <1.5%
• Configuration: Two SFP chambers, one CMP station, and two wet-etch/clean stations supporting various chemistries (electrolytes, copper slurry, etchants).

The Ultra SFP offers a safer, greener, and more cost-effective alternative to traditional CMP workflows for next-generation packaging technologies.

Please, Log in or Register to view URLs content!

 

[tokenanalyst]

Advanced Micro-Fabrication Equipment Inc. (AMEC) has been granted an invention patent for: "Plasma confinement ring, plasma processing equipment, and method for processing semiconductors".​

AMEC has been granted a new invention patent, entitled "Plasma Confinement Ring, Plasma Processing Equipment and Method for Processing Semiconductors", with patent application number CN202110723909 and authorization date of March 20, 2026.

Patent Abstract: This invention discloses a plasma confinement ring, a plasma processing device, and a method for processing semiconductors. The plasma confinement ring is disposed within the reaction chamber of the plasma processing device. The plasma confinement ring includes an annular sidewall and a gas channel wall fixedly connected to the annular sidewall. The annular sidewall is placed on a support ring, which is fixed to the sidewall of the reaction chamber. A heat insulation gap is disposed in the annular sidewall to slow down the transfer of heat from the gas channel wall to the sidewall of the reaction chamber. This invention enables the temperature of the plasma confinement ring to reach and maintain a preset temperature, thereby preventing polymer deposition.​

 

[tokenanalyst]

SEU-Hardened High-Speed SRAM Design with Self-Refresh and Adjacent-Bit Error Correction​

Abstract

This paper proposes a high-speed static random access memory (SRAM) architecture that integrates a self-refresh mechanism with a novel single error and adjacent-bit errors correction (SEABEC) scheme to enhance resilience against single-event upsets (SEUs) in radiation-prone environments. By leveraging extended Hamming coding and dynamic circuits, the design achieves a 29.1% RW speed improvement, reduces SEU cross-section by one order of magnitude, and incurs a 29.8% area overhead and a 95.2% dynamic power increase of the ECC module, leading to an overall chip area increase of ~14.2% compared to static logic-based RH SEC-DED SRAM. Radiation experiments validate superior tolerance across a LET range of 1.63–21.8 MeV·cm2/mg, demonstrating nearly doubled SEU resilience compared to conventional SEC-DED-based designs. This work balances error correction capabilities with system efficiency, making it suitable for high-reliability applications in space electronics and advanced processors.​

Please, Log in or Register to view URLs content!

 

[tokenanalyst]

View attachment 172184

close up

 

[PopularScience]

Breaking the global RISC-V CPU performance record! Alibaba DAMO Academy releases XuanTie C950

Single-core general performance exceeded 70 points in the SPECint2006 benchmark test.

Please, Log in or Register to view URLs content!

 

[interestedseal]

Please, Log in or Register to view URLs content!

First confirmation of Chinese 4kx4k HOT MWIR FPA (MCT?) being marketed in public. Looks like Teledyne started production around 2014? If they are only 10 years behind SOTA, that’s really not bad.

Please, Log in or Register to view URLs content!

Please, Log in or Register to view URLs content!

Built by L3Harris, the “large format” focal plane sensor — at 4,000 pixels by 4,000 pixels (4k X 4k) — will be able to track the infrared plumes of missiles over a wider swatch of the Earth at higher resolutions than SBIRS, Bogstie said, adding that it also will feature “reduced noise” in its signal.

I thought later versions of SBIRS already used 4kx4k FPA? Maybe not. But nextgen OPIR definitely will, the first one of which will be launched this year.

 

[tphuang]

https://twitter.com/i/web/status/2036429926866296853

more on the T-Head news today. They also released the C925 high efficiency core and now have a family of cores for SoC design. They've also partnered up with the people behind Xiangshan family of cores.