Chinese semiconductor industry

jfcarli said:

Quite frankly, my worries are not so much the money being spent with its engineers and workforce. The biggest problem, from my point of view, is keeping 10 to 12 thousand highly motivated people innactive.

If you don't throw those people very juicy bones to keep their teeth sharpened you are bound to lose them very quickly.

That is why I believe Hisilicon is making those people work double shiifts to circumvent the inexistance of EUV equipment in China, while still making top level SOCs.

That would demand a miracle and is definitely juicy enough to keep any engineer fully motivated. Making miracles is worthy of anybody's efforts and can keep you quite busy and happy with the bone.

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You aren't wrong...
Look how Taiwan is to trying to keep engineers "stuck" on the island, passing laws to make it illegal for them to look for work on the mainland.
The money SMIC has thrown at the former #2 and #3 of TSMC is crazy.
Intel is hiring all their old hands back to the company, I imagine it is not cheap either.

Once they are gone, it will take a lot more to get them back. If they get a US Green Card (which we can safely assume is a sure thing if they wanted it), then their opportunities become even broader.

The HiSilicon team has already proven themselves, the Kirin processors are usually top performers trading blows with Snapdragon in performance on the same generation of ARM IP-core. It is ahead of the Samsung Exynos team. If these guys are up for grabs, who wouldn't want to poach them?

ansy1968 said:

@BoraTas thanks sir for explaining it in layman terms, I learned a lot, since we are on the subject of 3D chiplets, can it also be done using EUVL? or it will be redundant?

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I am sure you can combine both of them for even higher performance.

jfcarli said:

Quite frankly, my worries are not so much the money being spent with its engineers and workforce. The biggest problem, from my point of view, is keeping 10 to 12 thousand highly motivated people innactive.

If you don't throw those people very juicy bones to keep their teeth sharpened you are bound to lose them very quickly.

That is why I believe Hisilicon is making those people work double shiifts to circumvent the inexistance of EUV equipment in China, while still making top level SOCs.

That would demand a miracle and is definitely juicy enough to keep any engineer fully motivated. Making miracles is worthy of anybody's efforts and can keep you quite busy and happy with the bone.

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Those engineers have never been more busy. They are working on RISC-V, Loongson and other techs that will completely eliminate American choke points.
They are on war fighting mode and they are baying for blood.
Expect Huawei to shock everyone in two three years. They'll be back better and will be hard to ignore them.
The same way they displaced everyone on their way to dominating 4G and 5G will be repeated in every sector they set their sights on.
Build Big Better will be Huawei not America

Topazchen said:

Those engineers have never been more busy. They are working on RISC-V, Loongson and other techs that will completely eliminate American choke points.
They are on war fighting mode and they are baying for blood.
Expect Huawei to shock everyone in two three years. They'll be back better and will be hard to ignore them.
The same way they displaced everyone on their way to dominating 4G and 5G will be repeated in every sector they set their sights on.
Build Big Better will be Huawei not America

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"...they are baying for blood."

I like that!

BoraTas said:

It is unlikely that anyone will achieve a completely 3D stacked SOC anytime soon without decreasing clock rates. Especially, control units and execution units in CPUs are very active circuits which causes them to generate a lot of heat. Less active parts on the chip like L2 and L3 caches, system agent, etc may be stacked though. 3D stacking of less active parts may free more space for active parts like first-level caches, execution units, and control units. This is very important because a larger die always means a much higher price. 3D stacking and chiplets may allow Huawei to incorporate the same or even more number of transistors compared to a conventional 5 nm chip at the same prices while using a larger node.

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The reason smaller node size is important is not because of transistor density but transistor efficiency. You can pack as many extra transistors into a space as you want but it won’t change the fact that you’re still not matching performance per watt.

latenlazy said:

The reason smaller node size is important is not because of transistor density but transistor efficiency. You can pack as many extra transistors into a space as you want but it won’t change the fact that you’re still not matching performance per watt.

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True. But that is a much easier problem to solve. Even if you fail in implementing better power-saving solutions you can still just install a 10% larger battery.

latenlazy said:

The reason smaller node size is important is not because of transistor density but transistor efficiency. You can pack as many extra transistors into a space as you want but it won’t change the fact that you’re still not matching performance per watt.

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This is why there's a push for smaller node sizes in (mostly) smartphone and PC without the corresponding push in communications/server since smartphone and PC often don't have external power sources but base stations always do. Always preferable to be more efficient, nevertheless, the main industrial bottlenecks are smaller once you have higher nodes with external power

BoraTas said:

True. But that is a much easier problem to solve. Even if you fail in implementing better power-saving solutions you can still just install a 10% larger battery.

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Efficiency matters not just because of compute per watt but because of heat. If your transistors get hot they become less efficient, both in power consumption *and* in compute power. The feedback loop between greater heat from faster computes and power consumption and compute power degradation from greater heat puts an upper cap to applications that can't employ aggressive cooling solutions. This is why supercomputers and desktops can get away with using larger process nodes, graphic cards and baseband stations greatly benefit from smaller nodes even when they can be designed around using larger nodes, and high compute power microelectronics are hard capped by process node iteration.

latenlazy said:

Efficiency matters not just because of compute per watt but because of heat. If your transistors get hot they become less efficient, both in power consumption *and* in compute power. The feedback loop between greater heat from faster computes and power consumption and compute power degradation from greater heat puts an upper cap to applications that can't employ aggressive cooling solutions. This is why supercomputers and desktops can get away with using larger process nodes, graphic cards and baseband stations greatly benefit from smaller nodes even when they can be designed around using larger nodes, and high compute power microelectronics are hard capped by process node iteration.

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Wrong. Silicon actually has both lower capacitance and resistivity in higher temperatures. As long as you don't go above 100 degrees most modern CPUs don't even decrease their clock speed. Node size is important for sure but other optimizations can make up for small deficiencies in node size especially in this era when performance increase per node shrink is around 15%. It is not like we are comparing 600 nm to 5 nm here. We are comparing a 7 nm chip to a 5/3 nm one.

BoraTas said:

Wrong. Silicon actually has both lower capacitance and resistivity in higher temperatures. As long as you don't go above 100 degrees most modern CPUs don't even decrease their clock speed. Node size is important for sure but other optimizations can make up for small deficiencies in node size especially in this era when performance increase per node shrink is around 15%. It is not like we are comparing 600 nm to 5 nm here. We are comparing a 7 nm chip to a 5/3 nm one.

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The measure of your compute effiency isn’t measured by your capacitance and resistivity. It’s measured in your electron loss during switching operations. Lower resistivity means for each switching operations you are letting more electrons through per switch, which is *bad* for compute efficiency and heat and power consumption. You want to pass through less electrons per switch, if possible. That’s what drives performance. Transistor efficiency is *all* about trying to do more work with fewer electron.

So long as your processor doesn’t go over 100 degrees is a huge caveat. Even everyday consumer processors when doing heavy loads can actually go beyond that temperature quite easily. Remember, what matters for your transistor efficiency is the *local* temperature, and that is specifically the local temperature in a very small area. Your whole device doesn’t need to be at 100 degrees for your processor to be. When your device is heating to 30 or even 40 degrees C it’s basically heat sinking for the thermal load generated by your processor. If your whole device, representing a much bigger area, can get that hot from absorbing the heat from your processor, that’s telling you a lot about how hot your processor, the generator of the heat, is actually getting.

You can try to finagle around the difference in performance for each node shrink as much as you want but the figures are what they are. When they say a node shrink gives 15-20% more compute or 15-30% less power consumption, those figures are what they are, and if you’re two nodes behind those differences *compound*. 60 microns to 6 nanometers may represent a performance difference of many multiples, and that’s certainly not the level of difference we’re talking about, but a 30-50% difference in performance (compounded across two or three nodes of performance gains) is nothing to sneeze at either.