It is unlikely that anyone will achieve a completely 3D stacked SOC anytime soon without decreasing clock rates. Especially, control units and execution units in CPUs are very active circuits which causes them to generate a lot of heat. Less active parts on the chip like L2 and L3 caches, system agent, etc may be stacked though. 3D stacking of less active parts may free more space for active parts like first-level caches, execution units, and control units. This is very important because a larger die always means a much higher price. 3D stacking and chiplets may allow Huawei to incorporate the same or even more number of transistors compared to a conventional 5 nm chip at the same prices while using a larger node.