@krautmeister bro good day, need your opinion, regarding SMIC 7nm risk production since last April, "No news means good news" and the risk production is doing well? the silence is deafening. My hypothesis like everything about China is that the announcement will follow when the preparation or a contingency plan is in place.. Maybe next year when the domestic equivalent is in operation.
Your guess is as good as mine. What we do know is that SMIC N+2 started trials sometime after N+1 taped out end of 2020. So, at some point this year, N+2, aka, their equivalent 7nm process, is going to be ready for risk production as their N+1 ramps some level of mass production. Latest word is that their N+1 process still has low yields and is the reason why it's still in trial production. My guess is that SMIC is currently integrating all fully mature domestic components from the domestic supply chain, as well as removing any American origin components.
All other 7nm work is secret. The procession from 14nm to 7nm is FINFET immersion DUV dual patterning to quad patterning. This is technically way easier than jumping from 28nm planar to 12-20nm FINFET because FINFET is the first "3D" transistor design where multi-patterning is used along with many more masks and exposures. This kind of expertise is "relatively" rare, especially in China. So, once a 14nm FINFET process node is achieved, meaning going over the expertise hump, jumping from 14nm to 7nm should be "relatively" easy. Take the example of HLMC. HLMC has been promising their 14nm FINFET node since mid-2019 and it's now over 2 years late and still in "quality acceptance" as they call it, aka. trial production.
SMIC already has their own 14nm FINFET process node yielding in the 90-95% range. Imo, 7nm DUV can be
commercially viable with a fully China domestic supply chain even vs 7nm EUV produced
outside China. The bigger question is how long will it take? I have a hard time believing the recent reports suggesting trial production of a fully domestic 7nm process by end of 2022. The first thing to confirm is whether all the rumors are real. That means we need to see delivery of an actual immersion lithography machine. Once we have this, then it's smooth sailing all the way to 7nm.
The main issue with DUV 7nm is that it is the process node where the cost-efficiency economics of DUV crosses over with EUV. The ASML Twinscan NXT DUV machines process 300mm wafers at something between 275-295 wafers per hour while the ASML NXE EUV models process at 100-125 wafers per hour. When you do the calculations on the economics of a quad-patterned DUV 7nm chip vs an EUV 7nm chip that uses fewer masks, exposures, chemicals, the EUV process cycle comes out cheaper even after the much higher initial capital cost of the EUV lithography machine. This isn't even considering the superior power / performance characteristics of EUV chips at the same equivalent DUV process node. If a fab can retain an EUV machine in production long enough to fully depreciate the capital cost, then the economics really start favoring EUV chips.