They're probably referring to the Jasminer chip with hybrid bonded logic and DRAM. That said, seeing these techniques applied to AI chips is when things will get really exciting.This news says that China already produce hybrid bonding DRAM. I wonder which company is it？
Hybrid bonding could be applied to DRAM, analyst say
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DRAMs launching in the future may be made with hybrid bonding applied, a TechInsights analyst said on Thursday.
This is because it will allow chipmakers to increase the density of the DRAM to increase their capacity, analyst Jeongdong Choe said during a seminar hosted by SEMI in Suwon, south of Seoul.
LPDDR5X and other latest memory chips only had a cell array efficiency of 50% at the current stage, Choe said.
If like NAND, chipmakers can make the DRAM array die and make the peripheral separately, this could maximize density, he said.
Peripheral handles logic work in a DRAM. Current DRAM includes the logic circuits inside it. Choe is proposing that this be separated so that the space can be used to pack in more memory circuits.
NAND chips already have the peripheral underneath the memory cell to increase their densities.
Hybrid bonding refers to the bonding of a heterogeneous die and the wafer allowing improvements in I/O and circuit lengths.
Samsung, SK Hynix, and Intel are preparing to apply the process in their chip-making, according to analysts.
Choe said in China, products that have the CMOS logic and DRAM die hybrid bonded have already been produced and launched in the market.
Samsung and SK Hynix could make 32Gb DRAM using this same method, he said.
Meanwhile, the analyst also said that 3D DRAM is difficult to develop as unlike gate-all-around NAND __ a 3D NAND __ DRAM faces homogeneity issues if made in 3D
That is why memory chip makers will likely develop 4F square instead for the upgrade.
Samsung is developing 4F square memory chips while SK Hynix and Micron are focusing on 3D DRAM. 4F square is a cell array structure that is an upgrade from 6F square and can reduce the surface area of the die by 30%, according to analysts.
Chinese semiconductor industry
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They're probably referring to the Jasminer chip with hybrid bonded logic and DRAM. That said, seeing these techniques applied to AI chips is when things will get really exciting.
Atomic force microscope (AFM) is another metrology tool type that’s rarely talked about. It uses a tiny probe to directly measure the wafer surface and creates a map of surface roughness or topography. Parker system from South Korea is a market leader in this niche field, but there’s also a domestic alternative!
This is just the Russians making their own Loongson architecture Linux distro. It probably uses code already submitted by Loongson to the original projects or publicly available patches. The relevance of this is that the Russian government requires the use of software in the Russian software registry in government acquisitions. Also software must be in the Russian software registry in order for Russian companies (public or private) to get tax exemptions on software purchases. To be in the registry the software is supposed to have a support team located in Russia which has access to the source code so they can support it. Software which meets these criteria gets a tax exemption. This is a big deal if you want to sell to the corporate market in Russia in general.
That explains how the 3A6000 can have the same performance as the Intel i3 processor despite having a lower clock rate. It is 50% more wide.
The problem is, if they already hit the limits in terms of width of the architecture, how are they going to increase performance further to compete against latest generation US processors? Make a processor with a longer pipeline so they can reach a higher clockspeed? Further increasing issue width requires a compiler good enough to extract ILP from the code in the first place.
That's the size of the Reorder Buffer for Out of Order execution.
If you want a yardstick to compare against, these are the specs for the AMD Zen microarchitectures.
If they want to design a new core again with same process first that explains why they don't expect it to happen until 2 years have passed. They want to design the processor with the new core in same process first and deliver that next year, then shrink that processor the year after that.
That probably means they improved the design somehow. Perhaps by using more modern layout tools or smaller area cache memory cells. Since the width has increased by 50% and they added SMT (2 threads per core) there should have been some increase in chip size. Since there isn't, they must have improved design or process in some way.
The Intel processor has more cores. Just replicating the cores with their associated cache will lead to a total processor cache increase.
It would be nice if they figured out a way to reduce the size of the transistors and memory cells similar to what TSMC did for AMD with Zen 4c. But this would require work by SMIC which I doubt they will do.
They do get some government support. They must, since Loongson is used for example in the Beidou satellites. I wouldn't be surprised if it was used in military and machine control systems as well.
The Chinese commercial market hasn't responded because of cost/performance issues. But the Chinese government uses their products. With the increase in demand for Chinese designed and made computer hardware in recent years due to Chinese government orders, there has been a shortage of components to make government computers, which is why I think the Chinese government stopped the export of Loongson's chips. This wasn't targeted at Russia, the export ban was just to meet government demand. But I guess that Loongson and the Russian companies or government lobbied the Chinese government hard enough that they allowed exports to Russia to resume. This is a good thing, I think, since it might allow Loongson to gain traction in the export market. Something which thus far they have failed to do.
If Loongson also wants to reach higher market share worldwide I think they should license their ISA to 3rd parties. Otherwise I think a lot of non-US customers will eventually just move to RISC-V regardless of how good their chip implementations are. Even then long term success is hardly guaranteed.
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In case you want to get the short version of how this is supposed to work. You put the logic and memory cell areas of the DRAM in different wafers, and then you bond those wafers together to make a DRAM chip. The article claims this leads to a 50% DRAM chip area reduction. This is similar to how YMTC makes the memory cells for 3D NAND in different wafers from the logic and then bonds them together.
So basically they want to redesign the memory cells themselves to be smaller as well. And they expect a further 30% reduction in die size from that. Neat.
broadsword
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Why didn't they develop an octa-core 3A6000?
Probably to increase yield they launched the quad core first. But they do have a sixteen core 3A5000 dubbed the 3C5000L. So you should see higher core versions with this architecture eventually.
They seem to be a fabless company. Not clear who is their foundry partner. In these times this is not a small detail.
They are part of Tsinghua Unigroup (Beijing Zhiguangxin Holding), like UNISOC
On the technology side, they have a product, so they are quite advanced already.
I started reading this awesome thread. WOW
It is so exciting to follow China's semiconductor industry !
Every day, breakthrough !
It is so exciting to follow China's semiconductor industry !
Every day, breakthrough !
Source?
Seriously, you give the vibes of a troll trying to derail this thread with spam, posing as overly optimistic.
Might want to avoid unfounded claims.
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